| 1 | /*
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| 2 | * Copyright (c) 2005 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup ia64
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #ifndef KERN_ia64_CPU_H_
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| 36 | #define KERN_ia64_CPU_H_
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| 37 |
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| 38 | #include <arch/types.h>
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| 39 | #include <arch/register.h>
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| 40 | #include <arch/asm.h>
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| 41 | #include <arch/bootinfo.h>
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| 42 |
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| 43 | #define FAMILY_ITANIUM 0x7
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| 44 | #define FAMILY_ITANIUM2 0x1f
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| 45 |
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| 46 | typedef struct {
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| 47 | uint64_t cpuid0;
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| 48 | uint64_t cpuid1;
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| 49 | cpuid3_t cpuid3;
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| 50 | } cpu_arch_t;
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| 51 |
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| 52 | /** Read CPUID register.
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| 53 | *
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| 54 | * @param n CPUID register number.
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| 55 | *
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| 56 | * @return Value of CPUID[n] register.
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| 57 | */
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| 58 | static inline uint64_t cpuid_read(int n)
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| 59 | {
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| 60 | uint64_t v;
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| 61 |
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| 62 | asm volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
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| 63 |
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| 64 | return v;
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| 65 | }
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| 66 |
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| 67 |
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| 68 | #define CR64_ID_SHIFT 24
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| 69 | #define CR64_ID_MASK 0xff000000
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| 70 | #define CR64_EID_SHIFT 16
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| 71 | #define CR64_EID_MASK 0xff0000
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| 72 |
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| 73 | static inline int ia64_get_cpu_id(void)
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| 74 | {
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| 75 | uint64_t cr64=cr64_read();
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| 76 | return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
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| 77 | }
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| 78 |
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| 79 | static inline int ia64_get_cpu_eid(void)
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| 80 | {
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| 81 | uint64_t cr64=cr64_read();
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| 82 | return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
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| 83 | }
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| 84 |
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| 85 |
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| 86 | static inline void ipi_send_ipi(int id, int eid, int intno)
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| 87 | {
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| 88 | (bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
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| 89 | srlz_d();
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| 90 |
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| 91 | }
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| 92 |
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| 93 | #endif
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| 94 |
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| 95 | /** @}
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| 96 | */
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