source: mainline/kernel/arch/ia64/include/asm.h@ ec8c622

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ec8c622 was 22f0561, checked in by Jakub Jermar <jakub@…>, 14 years ago

Get rid of kernel static non-identity mappings on ia64.

  • IO_OFFSET is replaced by legacyio_virt_base and LEGACYIO_USER_BASE.
  • VIO_OFFSET and FW_OFFSET are removed entirely.
  • Legacy I/O and IO SAPIC are mapped via hw_map().
  • Remove corresponding locked translation records.
  • Cleanup ia64 kernel pio_read/write_8|16|32().
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_ASM_H_
36#define KERN_ia64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/register.h>
41#include <arch/legacyio.h>
42#include <trace.h>
43
44#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
45
46/** Map the I/O port address to a legacy I/O address. */
47NO_TRACE static inline uintptr_t p2a(volatile void *p)
48{
49 uintptr_t prt = (uintptr_t) p;
50
51 return legacyio_virt_base + (((prt >> 2) << 12) | (prt & 0xfff));
52}
53
54NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
55{
56 if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
57 *((ioport8_t *) p2a(port)) = v;
58 else
59 *port = v;
60
61 asm volatile (
62 "mf\n"
63 ::: "memory"
64 );
65}
66
67NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
68{
69 if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
70 *((ioport16_t *) p2a(port)) = v;
71 else
72 *port = v;
73
74 asm volatile (
75 "mf\n"
76 ::: "memory"
77 );
78}
79
80NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
81{
82 if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
83 *((ioport32_t *) p2a(port)) = v;
84 else
85 *port = v;
86
87 asm volatile (
88 "mf\n"
89 ::: "memory"
90 );
91}
92
93NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
94{
95 uint8_t v;
96
97 asm volatile (
98 "mf\n"
99 ::: "memory"
100 );
101
102 if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
103 v = *((ioport8_t *) p2a(port));
104 else
105 v = *port;
106
107 return v;
108}
109
110NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
111{
112 uint16_t v;
113
114 asm volatile (
115 "mf\n"
116 ::: "memory"
117 );
118
119 if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
120 v = *((ioport16_t *) p2a(port));
121 else
122 v = *port;
123
124 return v;
125}
126
127NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
128{
129 uint32_t v;
130
131 asm volatile (
132 "mf\n"
133 ::: "memory"
134 );
135
136 if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
137 v = *((ioport32_t *) p2a(port));
138 else
139 v = *port;
140
141 return v;
142}
143
144/** Return base address of current memory stack.
145 *
146 * The memory stack is assumed to be STACK_SIZE / 2 long. Note that there is
147 * also the RSE stack, which takes up the upper half of STACK_SIZE.
148 * The memory stack must start on page boundary.
149 */
150NO_TRACE static inline uintptr_t get_stack_base(void)
151{
152 uint64_t value;
153
154 asm volatile (
155 "mov %[value] = r12"
156 : [value] "=r" (value)
157 );
158
159 return (value & (~(STACK_SIZE / 2 - 1)));
160}
161
162/** Return Processor State Register.
163 *
164 * @return PSR.
165 *
166 */
167NO_TRACE static inline uint64_t psr_read(void)
168{
169 uint64_t v;
170
171 asm volatile (
172 "mov %[value] = psr\n"
173 : [value] "=r" (v)
174 );
175
176 return v;
177}
178
179/** Read IVA (Interruption Vector Address).
180 *
181 * @return Return location of interruption vector table.
182 *
183 */
184NO_TRACE static inline uint64_t iva_read(void)
185{
186 uint64_t v;
187
188 asm volatile (
189 "mov %[value] = cr.iva\n"
190 : [value] "=r" (v)
191 );
192
193 return v;
194}
195
196/** Write IVA (Interruption Vector Address) register.
197 *
198 * @param v New location of interruption vector table.
199 *
200 */
201NO_TRACE static inline void iva_write(uint64_t v)
202{
203 asm volatile (
204 "mov cr.iva = %[value]\n"
205 :: [value] "r" (v)
206 );
207}
208
209/** Read IVR (External Interrupt Vector Register).
210 *
211 * @return Highest priority, pending, unmasked external
212 * interrupt vector.
213 *
214 */
215NO_TRACE static inline uint64_t ivr_read(void)
216{
217 uint64_t v;
218
219 asm volatile (
220 "mov %[value] = cr.ivr\n"
221 : [value] "=r" (v)
222 );
223
224 return v;
225}
226
227NO_TRACE static inline uint64_t cr64_read(void)
228{
229 uint64_t v;
230
231 asm volatile (
232 "mov %[value] = cr64\n"
233 : [value] "=r" (v)
234 );
235
236 return v;
237}
238
239/** Write ITC (Interval Timer Counter) register.
240 *
241 * @param v New counter value.
242 *
243 */
244NO_TRACE static inline void itc_write(uint64_t v)
245{
246 asm volatile (
247 "mov ar.itc = %[value]\n"
248 :: [value] "r" (v)
249 );
250}
251
252/** Read ITC (Interval Timer Counter) register.
253 *
254 * @return Current counter value.
255 *
256 */
257NO_TRACE static inline uint64_t itc_read(void)
258{
259 uint64_t v;
260
261 asm volatile (
262 "mov %[value] = ar.itc\n"
263 : [value] "=r" (v)
264 );
265
266 return v;
267}
268
269/** Write ITM (Interval Timer Match) register.
270 *
271 * @param v New match value.
272 *
273 */
274NO_TRACE static inline void itm_write(uint64_t v)
275{
276 asm volatile (
277 "mov cr.itm = %[value]\n"
278 :: [value] "r" (v)
279 );
280}
281
282/** Read ITM (Interval Timer Match) register.
283 *
284 * @return Match value.
285 *
286 */
287NO_TRACE static inline uint64_t itm_read(void)
288{
289 uint64_t v;
290
291 asm volatile (
292 "mov %[value] = cr.itm\n"
293 : [value] "=r" (v)
294 );
295
296 return v;
297}
298
299/** Read ITV (Interval Timer Vector) register.
300 *
301 * @return Current vector and mask bit.
302 *
303 */
304NO_TRACE static inline uint64_t itv_read(void)
305{
306 uint64_t v;
307
308 asm volatile (
309 "mov %[value] = cr.itv\n"
310 : [value] "=r" (v)
311 );
312
313 return v;
314}
315
316/** Write ITV (Interval Timer Vector) register.
317 *
318 * @param v New vector and mask bit.
319 *
320 */
321NO_TRACE static inline void itv_write(uint64_t v)
322{
323 asm volatile (
324 "mov cr.itv = %[value]\n"
325 :: [value] "r" (v)
326 );
327}
328
329/** Write EOI (End Of Interrupt) register.
330 *
331 * @param v This value is ignored.
332 *
333 */
334NO_TRACE static inline void eoi_write(uint64_t v)
335{
336 asm volatile (
337 "mov cr.eoi = %[value]\n"
338 :: [value] "r" (v)
339 );
340}
341
342/** Read TPR (Task Priority Register).
343 *
344 * @return Current value of TPR.
345 *
346 */
347NO_TRACE static inline uint64_t tpr_read(void)
348{
349 uint64_t v;
350
351 asm volatile (
352 "mov %[value] = cr.tpr\n"
353 : [value] "=r" (v)
354 );
355
356 return v;
357}
358
359/** Write TPR (Task Priority Register).
360 *
361 * @param v New value of TPR.
362 *
363 */
364NO_TRACE static inline void tpr_write(uint64_t v)
365{
366 asm volatile (
367 "mov cr.tpr = %[value]\n"
368 :: [value] "r" (v)
369 );
370}
371
372/** Disable interrupts.
373 *
374 * Disable interrupts and return previous
375 * value of PSR.
376 *
377 * @return Old interrupt priority level.
378 *
379 */
380NO_TRACE static ipl_t interrupts_disable(void)
381{
382 uint64_t v;
383
384 asm volatile (
385 "mov %[value] = psr\n"
386 "rsm %[mask]\n"
387 : [value] "=r" (v)
388 : [mask] "i" (PSR_I_MASK)
389 );
390
391 return (ipl_t) v;
392}
393
394/** Enable interrupts.
395 *
396 * Enable interrupts and return previous
397 * value of PSR.
398 *
399 * @return Old interrupt priority level.
400 *
401 */
402NO_TRACE static ipl_t interrupts_enable(void)
403{
404 uint64_t v;
405
406 asm volatile (
407 "mov %[value] = psr\n"
408 "ssm %[mask]\n"
409 ";;\n"
410 "srlz.d\n"
411 : [value] "=r" (v)
412 : [mask] "i" (PSR_I_MASK)
413 );
414
415 return (ipl_t) v;
416}
417
418/** Restore interrupt priority level.
419 *
420 * Restore PSR.
421 *
422 * @param ipl Saved interrupt priority level.
423 *
424 */
425NO_TRACE static inline void interrupts_restore(ipl_t ipl)
426{
427 if (ipl & PSR_I_MASK)
428 (void) interrupts_enable();
429 else
430 (void) interrupts_disable();
431}
432
433/** Return interrupt priority level.
434 *
435 * @return PSR.
436 *
437 */
438NO_TRACE static inline ipl_t interrupts_read(void)
439{
440 return (ipl_t) psr_read();
441}
442
443/** Check interrupts state.
444 *
445 * @return True if interrupts are disabled.
446 *
447 */
448NO_TRACE static inline bool interrupts_disabled(void)
449{
450 return !(psr_read() & PSR_I_MASK);
451}
452
453/** Disable protection key checking. */
454NO_TRACE static inline void pk_disable(void)
455{
456 asm volatile (
457 "rsm %[mask]\n"
458 ";;\n"
459 "srlz.d\n"
460 :: [mask] "i" (PSR_PK_MASK)
461 );
462}
463
464extern void cpu_halt(void) __attribute__((noreturn));
465extern void cpu_sleep(void);
466extern void asm_delay_loop(uint32_t t);
467
468extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
469 uint64_t, uint64_t);
470
471#endif
472
473/** @}
474 */
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