source: mainline/kernel/arch/ia64/include/asm.h@ d8db519

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d8db519 was d8db519, checked in by Martin Decky <martin@…>, 14 years ago

update syscall prototypes
cleanup includes
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_ASM_H_
36#define KERN_ia64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <arch/register.h>
41#include <trace.h>
42
43#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
44
45#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
46
47NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
48{
49 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
50 uintptr_t prt = (uintptr_t) port;
51
52 *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
53 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
54 } else {
55 *port = v;
56 }
57
58 asm volatile (
59 "mf\n"
60 ::: "memory"
61 );
62}
63
64NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
65{
66 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
67 uintptr_t prt = (uintptr_t) port;
68
69 *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
70 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
71 } else {
72 *port = v;
73 }
74
75 asm volatile (
76 "mf\n"
77 ::: "memory"
78 );
79}
80
81NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
82{
83 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
84 uintptr_t prt = (uintptr_t) port;
85
86 *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
87 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
88 } else {
89 *port = v;
90 }
91
92 asm volatile (
93 "mf\n"
94 ::: "memory"
95 );
96}
97
98NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
99{
100 uint8_t v;
101
102 asm volatile (
103 "mf\n"
104 ::: "memory"
105 );
106
107 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
108 uintptr_t prt = (uintptr_t) port;
109
110 v = *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
111 ((prt & 0xfff) | ((prt >> 2) << 12))));
112 } else {
113 v = *port;
114 }
115
116 return v;
117}
118
119NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
120{
121 uint16_t v;
122
123 asm volatile (
124 "mf\n"
125 ::: "memory"
126 );
127
128 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
129 uintptr_t prt = (uintptr_t) port;
130
131 v = *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
132 ((prt & 0xfff) | ((prt >> 2) << 12))));
133 } else {
134 v = *port;
135 }
136
137 return v;
138}
139
140NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
141{
142 uint32_t v;
143
144 asm volatile (
145 "mf\n"
146 ::: "memory"
147 );
148
149 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
150 uintptr_t prt = (uintptr_t) port;
151
152 v = *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
153 ((prt & 0xfff) | ((prt >> 2) << 12))));
154 } else {
155 v = *port;
156 }
157
158 return v;
159}
160
161/** Return base address of current memory stack.
162 *
163 * The memory stack is assumed to be STACK_SIZE / 2 long. Note that there is
164 * also the RSE stack, which takes up the upper half of STACK_SIZE.
165 * The memory stack must start on page boundary.
166 */
167NO_TRACE static inline uintptr_t get_stack_base(void)
168{
169 uint64_t value;
170
171 asm volatile (
172 "mov %[value] = r12"
173 : [value] "=r" (value)
174 );
175
176 return (value & (~(STACK_SIZE / 2 - 1)));
177}
178
179/** Return Processor State Register.
180 *
181 * @return PSR.
182 *
183 */
184NO_TRACE static inline uint64_t psr_read(void)
185{
186 uint64_t v;
187
188 asm volatile (
189 "mov %[value] = psr\n"
190 : [value] "=r" (v)
191 );
192
193 return v;
194}
195
196/** Read IVA (Interruption Vector Address).
197 *
198 * @return Return location of interruption vector table.
199 *
200 */
201NO_TRACE static inline uint64_t iva_read(void)
202{
203 uint64_t v;
204
205 asm volatile (
206 "mov %[value] = cr.iva\n"
207 : [value] "=r" (v)
208 );
209
210 return v;
211}
212
213/** Write IVA (Interruption Vector Address) register.
214 *
215 * @param v New location of interruption vector table.
216 *
217 */
218NO_TRACE static inline void iva_write(uint64_t v)
219{
220 asm volatile (
221 "mov cr.iva = %[value]\n"
222 :: [value] "r" (v)
223 );
224}
225
226/** Read IVR (External Interrupt Vector Register).
227 *
228 * @return Highest priority, pending, unmasked external
229 * interrupt vector.
230 *
231 */
232NO_TRACE static inline uint64_t ivr_read(void)
233{
234 uint64_t v;
235
236 asm volatile (
237 "mov %[value] = cr.ivr\n"
238 : [value] "=r" (v)
239 );
240
241 return v;
242}
243
244NO_TRACE static inline uint64_t cr64_read(void)
245{
246 uint64_t v;
247
248 asm volatile (
249 "mov %[value] = cr64\n"
250 : [value] "=r" (v)
251 );
252
253 return v;
254}
255
256/** Write ITC (Interval Timer Counter) register.
257 *
258 * @param v New counter value.
259 *
260 */
261NO_TRACE static inline void itc_write(uint64_t v)
262{
263 asm volatile (
264 "mov ar.itc = %[value]\n"
265 :: [value] "r" (v)
266 );
267}
268
269/** Read ITC (Interval Timer Counter) register.
270 *
271 * @return Current counter value.
272 *
273 */
274NO_TRACE static inline uint64_t itc_read(void)
275{
276 uint64_t v;
277
278 asm volatile (
279 "mov %[value] = ar.itc\n"
280 : [value] "=r" (v)
281 );
282
283 return v;
284}
285
286/** Write ITM (Interval Timer Match) register.
287 *
288 * @param v New match value.
289 *
290 */
291NO_TRACE static inline void itm_write(uint64_t v)
292{
293 asm volatile (
294 "mov cr.itm = %[value]\n"
295 :: [value] "r" (v)
296 );
297}
298
299/** Read ITM (Interval Timer Match) register.
300 *
301 * @return Match value.
302 *
303 */
304NO_TRACE static inline uint64_t itm_read(void)
305{
306 uint64_t v;
307
308 asm volatile (
309 "mov %[value] = cr.itm\n"
310 : [value] "=r" (v)
311 );
312
313 return v;
314}
315
316/** Read ITV (Interval Timer Vector) register.
317 *
318 * @return Current vector and mask bit.
319 *
320 */
321NO_TRACE static inline uint64_t itv_read(void)
322{
323 uint64_t v;
324
325 asm volatile (
326 "mov %[value] = cr.itv\n"
327 : [value] "=r" (v)
328 );
329
330 return v;
331}
332
333/** Write ITV (Interval Timer Vector) register.
334 *
335 * @param v New vector and mask bit.
336 *
337 */
338NO_TRACE static inline void itv_write(uint64_t v)
339{
340 asm volatile (
341 "mov cr.itv = %[value]\n"
342 :: [value] "r" (v)
343 );
344}
345
346/** Write EOI (End Of Interrupt) register.
347 *
348 * @param v This value is ignored.
349 *
350 */
351NO_TRACE static inline void eoi_write(uint64_t v)
352{
353 asm volatile (
354 "mov cr.eoi = %[value]\n"
355 :: [value] "r" (v)
356 );
357}
358
359/** Read TPR (Task Priority Register).
360 *
361 * @return Current value of TPR.
362 *
363 */
364NO_TRACE static inline uint64_t tpr_read(void)
365{
366 uint64_t v;
367
368 asm volatile (
369 "mov %[value] = cr.tpr\n"
370 : [value] "=r" (v)
371 );
372
373 return v;
374}
375
376/** Write TPR (Task Priority Register).
377 *
378 * @param v New value of TPR.
379 *
380 */
381NO_TRACE static inline void tpr_write(uint64_t v)
382{
383 asm volatile (
384 "mov cr.tpr = %[value]\n"
385 :: [value] "r" (v)
386 );
387}
388
389/** Disable interrupts.
390 *
391 * Disable interrupts and return previous
392 * value of PSR.
393 *
394 * @return Old interrupt priority level.
395 *
396 */
397NO_TRACE static ipl_t interrupts_disable(void)
398{
399 uint64_t v;
400
401 asm volatile (
402 "mov %[value] = psr\n"
403 "rsm %[mask]\n"
404 : [value] "=r" (v)
405 : [mask] "i" (PSR_I_MASK)
406 );
407
408 return (ipl_t) v;
409}
410
411/** Enable interrupts.
412 *
413 * Enable interrupts and return previous
414 * value of PSR.
415 *
416 * @return Old interrupt priority level.
417 *
418 */
419NO_TRACE static ipl_t interrupts_enable(void)
420{
421 uint64_t v;
422
423 asm volatile (
424 "mov %[value] = psr\n"
425 "ssm %[mask]\n"
426 ";;\n"
427 "srlz.d\n"
428 : [value] "=r" (v)
429 : [mask] "i" (PSR_I_MASK)
430 );
431
432 return (ipl_t) v;
433}
434
435/** Restore interrupt priority level.
436 *
437 * Restore PSR.
438 *
439 * @param ipl Saved interrupt priority level.
440 *
441 */
442NO_TRACE static inline void interrupts_restore(ipl_t ipl)
443{
444 if (ipl & PSR_I_MASK)
445 (void) interrupts_enable();
446 else
447 (void) interrupts_disable();
448}
449
450/** Return interrupt priority level.
451 *
452 * @return PSR.
453 *
454 */
455NO_TRACE static inline ipl_t interrupts_read(void)
456{
457 return (ipl_t) psr_read();
458}
459
460/** Check interrupts state.
461 *
462 * @return True if interrupts are disabled.
463 *
464 */
465NO_TRACE static inline bool interrupts_disabled(void)
466{
467 return !(psr_read() & PSR_I_MASK);
468}
469
470/** Disable protection key checking. */
471NO_TRACE static inline void pk_disable(void)
472{
473 asm volatile (
474 "rsm %[mask]\n"
475 ";;\n"
476 "srlz.d\n"
477 :: [mask] "i" (PSR_PK_MASK)
478 );
479}
480
481extern void cpu_halt(void) __attribute__((noreturn));
482extern void cpu_sleep(void);
483extern void asm_delay_loop(uint32_t t);
484
485extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
486 uint64_t, uint64_t);
487
488#endif
489
490/** @}
491 */
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