source: mainline/kernel/arch/ia64/include/asm.h@ ddcc8a0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ddcc8a0 was 86a34d3e, checked in by Jakub Jermar <jakub@…>, 14 years ago

Make ia64 PIO functions usable with memory-mapped registers.
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 * Copyright (c) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia64
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_ia64_ASM_H_
36#define KERN_ia64_ASM_H_
37
38#include <config.h>
39#include <typedefs.h>
40#include <typedefs.h>
41#include <arch/register.h>
42#include <trace.h>
43
44#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
45
46#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
47
48NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
49{
50 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
51 uintptr_t prt = (uintptr_t) port;
52
53 *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
54 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
55 } else {
56 *port = v;
57 }
58
59 asm volatile (
60 "mf\n"
61 ::: "memory"
62 );
63}
64
65NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
66{
67 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
68 uintptr_t prt = (uintptr_t) port;
69
70 *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
71 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
72 } else {
73 *port = v;
74 }
75
76 asm volatile (
77 "mf\n"
78 ::: "memory"
79 );
80}
81
82NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
83{
84 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
85 uintptr_t prt = (uintptr_t) port;
86
87 *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
88 ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
89 } else {
90 *port = v;
91 }
92
93 asm volatile (
94 "mf\n"
95 ::: "memory"
96 );
97}
98
99NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
100{
101 uint8_t v;
102
103 asm volatile (
104 "mf\n"
105 ::: "memory"
106 );
107
108 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
109 uintptr_t prt = (uintptr_t) port;
110
111 v = *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
112 ((prt & 0xfff) | ((prt >> 2) << 12))));
113 } else {
114 v = *port;
115 }
116
117 return v;
118}
119
120NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
121{
122 uint16_t v;
123
124 asm volatile (
125 "mf\n"
126 ::: "memory"
127 );
128
129 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
130 uintptr_t prt = (uintptr_t) port;
131
132 v = *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
133 ((prt & 0xfff) | ((prt >> 2) << 12))));
134 } else {
135 v = *port;
136 }
137
138 return v;
139}
140
141NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
142{
143 uint32_t v;
144
145 asm volatile (
146 "mf\n"
147 ::: "memory"
148 );
149
150 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
151 uintptr_t prt = (uintptr_t) port;
152
153 v = *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
154 ((prt & 0xfff) | ((prt >> 2) << 12))));
155 } else {
156 v = *port;
157 }
158
159 return v;
160}
161
162/** Return base address of current memory stack.
163 *
164 * The memory stack is assumed to be STACK_SIZE / 2 long. Note that there is
165 * also the RSE stack, which takes up the upper half of STACK_SIZE.
166 * The memory stack must start on page boundary.
167 */
168NO_TRACE static inline uintptr_t get_stack_base(void)
169{
170 uint64_t value;
171
172 asm volatile (
173 "mov %[value] = r12"
174 : [value] "=r" (value)
175 );
176
177 return (value & (~(STACK_SIZE / 2 - 1)));
178}
179
180/** Return Processor State Register.
181 *
182 * @return PSR.
183 *
184 */
185NO_TRACE static inline uint64_t psr_read(void)
186{
187 uint64_t v;
188
189 asm volatile (
190 "mov %[value] = psr\n"
191 : [value] "=r" (v)
192 );
193
194 return v;
195}
196
197/** Read IVA (Interruption Vector Address).
198 *
199 * @return Return location of interruption vector table.
200 *
201 */
202NO_TRACE static inline uint64_t iva_read(void)
203{
204 uint64_t v;
205
206 asm volatile (
207 "mov %[value] = cr.iva\n"
208 : [value] "=r" (v)
209 );
210
211 return v;
212}
213
214/** Write IVA (Interruption Vector Address) register.
215 *
216 * @param v New location of interruption vector table.
217 *
218 */
219NO_TRACE static inline void iva_write(uint64_t v)
220{
221 asm volatile (
222 "mov cr.iva = %[value]\n"
223 :: [value] "r" (v)
224 );
225}
226
227/** Read IVR (External Interrupt Vector Register).
228 *
229 * @return Highest priority, pending, unmasked external
230 * interrupt vector.
231 *
232 */
233NO_TRACE static inline uint64_t ivr_read(void)
234{
235 uint64_t v;
236
237 asm volatile (
238 "mov %[value] = cr.ivr\n"
239 : [value] "=r" (v)
240 );
241
242 return v;
243}
244
245NO_TRACE static inline uint64_t cr64_read(void)
246{
247 uint64_t v;
248
249 asm volatile (
250 "mov %[value] = cr64\n"
251 : [value] "=r" (v)
252 );
253
254 return v;
255}
256
257/** Write ITC (Interval Timer Counter) register.
258 *
259 * @param v New counter value.
260 *
261 */
262NO_TRACE static inline void itc_write(uint64_t v)
263{
264 asm volatile (
265 "mov ar.itc = %[value]\n"
266 :: [value] "r" (v)
267 );
268}
269
270/** Read ITC (Interval Timer Counter) register.
271 *
272 * @return Current counter value.
273 *
274 */
275NO_TRACE static inline uint64_t itc_read(void)
276{
277 uint64_t v;
278
279 asm volatile (
280 "mov %[value] = ar.itc\n"
281 : [value] "=r" (v)
282 );
283
284 return v;
285}
286
287/** Write ITM (Interval Timer Match) register.
288 *
289 * @param v New match value.
290 *
291 */
292NO_TRACE static inline void itm_write(uint64_t v)
293{
294 asm volatile (
295 "mov cr.itm = %[value]\n"
296 :: [value] "r" (v)
297 );
298}
299
300/** Read ITM (Interval Timer Match) register.
301 *
302 * @return Match value.
303 *
304 */
305NO_TRACE static inline uint64_t itm_read(void)
306{
307 uint64_t v;
308
309 asm volatile (
310 "mov %[value] = cr.itm\n"
311 : [value] "=r" (v)
312 );
313
314 return v;
315}
316
317/** Read ITV (Interval Timer Vector) register.
318 *
319 * @return Current vector and mask bit.
320 *
321 */
322NO_TRACE static inline uint64_t itv_read(void)
323{
324 uint64_t v;
325
326 asm volatile (
327 "mov %[value] = cr.itv\n"
328 : [value] "=r" (v)
329 );
330
331 return v;
332}
333
334/** Write ITV (Interval Timer Vector) register.
335 *
336 * @param v New vector and mask bit.
337 *
338 */
339NO_TRACE static inline void itv_write(uint64_t v)
340{
341 asm volatile (
342 "mov cr.itv = %[value]\n"
343 :: [value] "r" (v)
344 );
345}
346
347/** Write EOI (End Of Interrupt) register.
348 *
349 * @param v This value is ignored.
350 *
351 */
352NO_TRACE static inline void eoi_write(uint64_t v)
353{
354 asm volatile (
355 "mov cr.eoi = %[value]\n"
356 :: [value] "r" (v)
357 );
358}
359
360/** Read TPR (Task Priority Register).
361 *
362 * @return Current value of TPR.
363 *
364 */
365NO_TRACE static inline uint64_t tpr_read(void)
366{
367 uint64_t v;
368
369 asm volatile (
370 "mov %[value] = cr.tpr\n"
371 : [value] "=r" (v)
372 );
373
374 return v;
375}
376
377/** Write TPR (Task Priority Register).
378 *
379 * @param v New value of TPR.
380 *
381 */
382NO_TRACE static inline void tpr_write(uint64_t v)
383{
384 asm volatile (
385 "mov cr.tpr = %[value]\n"
386 :: [value] "r" (v)
387 );
388}
389
390/** Disable interrupts.
391 *
392 * Disable interrupts and return previous
393 * value of PSR.
394 *
395 * @return Old interrupt priority level.
396 *
397 */
398NO_TRACE static ipl_t interrupts_disable(void)
399{
400 uint64_t v;
401
402 asm volatile (
403 "mov %[value] = psr\n"
404 "rsm %[mask]\n"
405 : [value] "=r" (v)
406 : [mask] "i" (PSR_I_MASK)
407 );
408
409 return (ipl_t) v;
410}
411
412/** Enable interrupts.
413 *
414 * Enable interrupts and return previous
415 * value of PSR.
416 *
417 * @return Old interrupt priority level.
418 *
419 */
420NO_TRACE static ipl_t interrupts_enable(void)
421{
422 uint64_t v;
423
424 asm volatile (
425 "mov %[value] = psr\n"
426 "ssm %[mask]\n"
427 ";;\n"
428 "srlz.d\n"
429 : [value] "=r" (v)
430 : [mask] "i" (PSR_I_MASK)
431 );
432
433 return (ipl_t) v;
434}
435
436/** Restore interrupt priority level.
437 *
438 * Restore PSR.
439 *
440 * @param ipl Saved interrupt priority level.
441 *
442 */
443NO_TRACE static inline void interrupts_restore(ipl_t ipl)
444{
445 if (ipl & PSR_I_MASK)
446 (void) interrupts_enable();
447 else
448 (void) interrupts_disable();
449}
450
451/** Return interrupt priority level.
452 *
453 * @return PSR.
454 *
455 */
456NO_TRACE static inline ipl_t interrupts_read(void)
457{
458 return (ipl_t) psr_read();
459}
460
461/** Check interrupts state.
462 *
463 * @return True if interrupts are disabled.
464 *
465 */
466NO_TRACE static inline bool interrupts_disabled(void)
467{
468 return !(psr_read() & PSR_I_MASK);
469}
470
471/** Disable protection key checking. */
472NO_TRACE static inline void pk_disable(void)
473{
474 asm volatile (
475 "rsm %[mask]\n"
476 ";;\n"
477 "srlz.d\n"
478 :: [mask] "i" (PSR_PK_MASK)
479 );
480}
481
482extern void cpu_halt(void) __attribute__((noreturn));
483extern void cpu_sleep(void);
484extern void asm_delay_loop(uint32_t t);
485
486extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
487 uint64_t, uint64_t);
488
489#endif
490
491/** @}
492 */
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