source: mainline/kernel/arch/ia32xen/src/smp/mps.c@ ca21eb4b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ca21eb4b was 6c441cf8, checked in by Martin Decky <martin@…>, 18 years ago

code cleanup (mostly signed/unsigned)
allow extra compiler warnings
  • Property mode set to 100644
File size: 10.3 KB
Line 
1/*
2 * Copyright (c) 2001-2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32xen
30 * @{
31 */
32/** @file
33 */
34
35#ifdef CONFIG_SMP
36
37#include <config.h>
38#include <print.h>
39#include <debug.h>
40#include <arch/smp/mps.h>
41#include <arch/smp/apic.h>
42#include <arch/smp/smp.h>
43#include <func.h>
44#include <arch/types.h>
45#include <cpu.h>
46#include <arch/asm.h>
47#include <arch/bios/bios.h>
48#include <mm/frame.h>
49
50/*
51 * MultiProcessor Specification detection code.
52 */
53
54#define FS_SIGNATURE 0x5f504d5f
55#define CT_SIGNATURE 0x504d4350
56
57int mps_fs_check(uint8_t *base);
58int mps_ct_check(void);
59
60int configure_via_ct(void);
61int configure_via_default(uint8_t n);
62
63int ct_processor_entry(struct __processor_entry *pr);
64void ct_bus_entry(struct __bus_entry *bus);
65void ct_io_apic_entry(struct __io_apic_entry *ioa);
66void ct_io_intr_entry(struct __io_intr_entry *iointr);
67void ct_l_intr_entry(struct __l_intr_entry *lintr);
68
69void ct_extended_entries(void);
70
71static struct mps_fs *fs;
72static struct mps_ct *ct;
73
74struct __processor_entry *processor_entries = NULL;
75struct __bus_entry *bus_entries = NULL;
76struct __io_apic_entry *io_apic_entries = NULL;
77struct __io_intr_entry *io_intr_entries = NULL;
78struct __l_intr_entry *l_intr_entries = NULL;
79
80unsigned int processor_entry_cnt = 0;
81unsigned int bus_entry_cnt = 0;
82unsigned int io_apic_entry_cnt = 0;
83unsigned int io_intr_entry_cnt = 0;
84unsigned int l_intr_entry_cnt = 0;
85
86waitq_t ap_completion_wq;
87
88/*
89 * Implementation of IA-32 SMP configuration interface.
90 */
91static count_t get_cpu_count(void);
92static bool is_cpu_enabled(index_t i);
93static bool is_bsp(index_t i);
94static uint8_t get_cpu_apic_id(index_t i);
95static int mps_irq_to_pin(unsigned int irq);
96
97struct smp_config_operations mps_config_operations = {
98 .cpu_count = get_cpu_count,
99 .cpu_enabled = is_cpu_enabled,
100 .cpu_bootstrap = is_bsp,
101 .cpu_apic_id = get_cpu_apic_id,
102 .irq_to_pin = mps_irq_to_pin
103};
104
105count_t get_cpu_count(void)
106{
107 return processor_entry_cnt;
108}
109
110bool is_cpu_enabled(index_t i)
111{
112 ASSERT(i < processor_entry_cnt);
113 return processor_entries[i].cpu_flags & 0x1;
114}
115
116bool is_bsp(index_t i)
117{
118 ASSERT(i < processor_entry_cnt);
119 return processor_entries[i].cpu_flags & 0x2;
120}
121
122uint8_t get_cpu_apic_id(index_t i)
123{
124 ASSERT(i < processor_entry_cnt);
125 return processor_entries[i].l_apic_id;
126}
127
128
129/*
130 * Used to check the integrity of the MP Floating Structure.
131 */
132int mps_fs_check(uint8_t *base)
133{
134 int i;
135 uint8_t sum;
136
137 for (i = 0, sum = 0; i < 16; i++)
138 sum += base[i];
139
140 return !sum;
141}
142
143/*
144 * Used to check the integrity of the MP Configuration Table.
145 */
146int mps_ct_check(void)
147{
148 uint8_t *base = (uint8_t *) ct;
149 uint8_t *ext = base + ct->base_table_length;
150 uint8_t sum;
151 int i;
152
153 /* count the checksum for the base table */
154 for (i=0,sum=0; i < ct->base_table_length; i++)
155 sum += base[i];
156
157 if (sum)
158 return 0;
159
160 /* count the checksum for the extended table */
161 for (i=0,sum=0; i < ct->ext_table_length; i++)
162 sum += ext[i];
163
164 return sum == ct->ext_table_checksum;
165}
166
167void mps_init(void)
168{
169 uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) };
170 int i, j, length[2] = { 1024, 64*1024 };
171
172
173 /*
174 * Find MP Floating Pointer Structure
175 * 1a. search first 1K of EBDA
176 * 1b. if EBDA is undefined, search last 1K of base memory
177 * 2. search 64K starting at 0xf0000
178 */
179
180 addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024);
181 for (i = 0; i < 2; i++) {
182 for (j = 0; j < length[i]; j += 16) {
183 if (*((uint32_t *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
184 fs = (struct mps_fs *) &addr[i][j];
185 goto fs_found;
186 }
187 }
188 }
189
190 return;
191
192fs_found:
193 printf("%p: MPS Floating Pointer Structure\n", fs);
194
195 if (fs->config_type == 0 && fs->configuration_table) {
196 if (fs->mpfib2 >> 7) {
197 printf("%s: PIC mode not supported\n", __func__);
198 return;
199 }
200
201 ct = (struct mps_ct *)PA2KA((uintptr_t)fs->configuration_table);
202 config.cpu_count = configure_via_ct();
203 }
204 else
205 config.cpu_count = configure_via_default(fs->config_type);
206
207 return;
208}
209
210int configure_via_ct(void)
211{
212 uint8_t *cur;
213 int i, cnt;
214
215 if (ct->signature != CT_SIGNATURE) {
216 printf("%s: bad ct->signature\n", __func__);
217 return 1;
218 }
219 if (!mps_ct_check()) {
220 printf("%s: bad ct checksum\n", __func__);
221 return 1;
222 }
223 if (ct->oem_table) {
224 printf("%s: ct->oem_table not supported\n", __func__);
225 return 1;
226 }
227
228 l_apic = (uint32_t *)(uintptr_t)ct->l_apic;
229
230 cnt = 0;
231 cur = &ct->base_table[0];
232 for (i=0; i < ct->entry_count; i++) {
233 switch (*cur) {
234 /* Processor entry */
235 case 0:
236 processor_entries = processor_entries ? processor_entries : (struct __processor_entry *) cur;
237 processor_entry_cnt++;
238 cnt += ct_processor_entry((struct __processor_entry *) cur);
239 cur += 20;
240 break;
241
242 /* Bus entry */
243 case 1:
244 bus_entries = bus_entries ? bus_entries : (struct __bus_entry *) cur;
245 bus_entry_cnt++;
246 ct_bus_entry((struct __bus_entry *) cur);
247 cur += 8;
248 break;
249
250 /* I/O Apic */
251 case 2:
252 io_apic_entries = io_apic_entries ? io_apic_entries : (struct __io_apic_entry *) cur;
253 io_apic_entry_cnt++;
254 ct_io_apic_entry((struct __io_apic_entry *) cur);
255 cur += 8;
256 break;
257
258 /* I/O Interrupt Assignment */
259 case 3:
260 io_intr_entries = io_intr_entries ? io_intr_entries : (struct __io_intr_entry *) cur;
261 io_intr_entry_cnt++;
262 ct_io_intr_entry((struct __io_intr_entry *) cur);
263 cur += 8;
264 break;
265
266 /* Local Interrupt Assignment */
267 case 4:
268 l_intr_entries = l_intr_entries ? l_intr_entries : (struct __l_intr_entry *) cur;
269 l_intr_entry_cnt++;
270 ct_l_intr_entry((struct __l_intr_entry *) cur);
271 cur += 8;
272 break;
273
274 default:
275 /*
276 * Something is wrong. Fallback to UP mode.
277 */
278
279 printf("%s: ct badness\n", __func__);
280 return 1;
281 }
282 }
283
284 /*
285 * Process extended entries.
286 */
287 ct_extended_entries();
288 return cnt;
289}
290
291int configure_via_default(uint8_t n)
292{
293 /*
294 * Not yet implemented.
295 */
296 printf("%s: not supported\n", __func__);
297 return 1;
298}
299
300
301int ct_processor_entry(struct __processor_entry *pr)
302{
303 /*
304 * Ignore processors which are not marked enabled.
305 */
306 if ((pr->cpu_flags & (1<<0)) == 0)
307 return 0;
308
309 apic_id_mask |= (1<<pr->l_apic_id);
310 return 1;
311}
312
313void ct_bus_entry(struct __bus_entry *bus)
314{
315#ifdef MPSCT_VERBOSE
316 char buf[7];
317 memcpy((void *) buf, (void *) bus->bus_type, 6);
318 buf[6] = 0;
319 printf("bus%d: %s\n", bus->bus_id, buf);
320#endif
321}
322
323void ct_io_apic_entry(struct __io_apic_entry *ioa)
324{
325 static int io_apic_count = 0;
326
327 /* this ioapic is marked unusable */
328 if ((ioa->io_apic_flags & 1) == 0)
329 return;
330
331 if (io_apic_count++ > 0) {
332 /*
333 * Multiple IO APIC's are currently not supported.
334 */
335 return;
336 }
337
338 io_apic = (uint32_t *)(uintptr_t)ioa->io_apic;
339}
340
341//#define MPSCT_VERBOSE
342void ct_io_intr_entry(struct __io_intr_entry *iointr)
343{
344#ifdef MPSCT_VERBOSE
345 switch (iointr->intr_type) {
346 case 0: printf("INT"); break;
347 case 1: printf("NMI"); break;
348 case 2: printf("SMI"); break;
349 case 3: printf("ExtINT"); break;
350 }
351 putchar(',');
352 switch (iointr->poel&3) {
353 case 0: printf("bus-like"); break;
354 case 1: printf("active high"); break;
355 case 2: printf("reserved"); break;
356 case 3: printf("active low"); break;
357 }
358 putchar(',');
359 switch ((iointr->poel>>2)&3) {
360 case 0: printf("bus-like"); break;
361 case 1: printf("edge-triggered"); break;
362 case 2: printf("reserved"); break;
363 case 3: printf("level-triggered"); break;
364 }
365 putchar(',');
366 printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq);
367 putchar(',');
368 printf("io_apic%d,pin%d", iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
369 putchar('\n');
370#endif
371}
372
373void ct_l_intr_entry(struct __l_intr_entry *lintr)
374{
375#ifdef MPSCT_VERBOSE
376 switch (lintr->intr_type) {
377 case 0: printf("INT"); break;
378 case 1: printf("NMI"); break;
379 case 2: printf("SMI"); break;
380 case 3: printf("ExtINT"); break;
381 }
382 putchar(',');
383 switch (lintr->poel&3) {
384 case 0: printf("bus-like"); break;
385 case 1: printf("active high"); break;
386 case 2: printf("reserved"); break;
387 case 3: printf("active low"); break;
388 }
389 putchar(',');
390 switch ((lintr->poel>>2)&3) {
391 case 0: printf("bus-like"); break;
392 case 1: printf("edge-triggered"); break;
393 case 2: printf("reserved"); break;
394 case 3: printf("level-triggered"); break;
395 }
396 putchar(',');
397 printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq);
398 putchar(',');
399 printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
400 putchar('\n');
401#endif
402}
403
404void ct_extended_entries(void)
405{
406 uint8_t *ext = (uint8_t *) ct + ct->base_table_length;
407 uint8_t *cur;
408
409 for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) {
410 switch (cur[CT_EXT_ENTRY_TYPE]) {
411 default:
412 printf("%p: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
413 break;
414 }
415 }
416}
417
418int mps_irq_to_pin(unsigned int irq)
419{
420 unsigned int i;
421
422 for (i = 0; i < io_intr_entry_cnt; i++) {
423 if (io_intr_entries[i].src_bus_irq == irq && io_intr_entries[i].intr_type == 0)
424 return io_intr_entries[i].dst_io_apic_pin;
425 }
426
427 return -1;
428}
429
430#endif /* CONFIG_SMP */
431
432/** @}
433 */
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