source: mainline/kernel/arch/ia32xen/src/smp/apic.c@ 44bec47

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 44bec47 was 566f5e5c, checked in by Jakub Jermar <jakub@…>, 18 years ago

Fix ia32xen so that it can be built.
  • Property mode set to 100644
File size: 13.4 KB
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[983cd374]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[983cd374]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[57ce359]29/** @addtogroup ia32xen
[983cd374]30 * @{
31 */
32/** @file
33 */
34
35#include <arch/types.h>
36#include <arch/smp/apic.h>
37#include <arch/smp/ap.h>
38#include <arch/smp/mps.h>
39#include <mm/page.h>
40#include <time/delay.h>
41#include <interrupt.h>
42#include <arch/interrupt.h>
43#include <print.h>
44#include <arch/asm.h>
45#include <arch.h>
46
47#ifdef CONFIG_SMP
48
49/*
50 * Advanced Programmable Interrupt Controller for SMP systems.
51 * Tested on:
52 * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
53 * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
54 * VMware Workstation 5.5 with 2 CPUs
55 * QEMU 0.8.0 with 2-15 CPUs
56 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
57 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
58 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
59 */
60
61/*
62 * These variables either stay configured as initilalized, or are changed by
63 * the MP configuration code.
64 *
65 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
66 * optimize the code too much and accesses to l_apic and io_apic, that must
67 * always be 32-bit, would use byte oriented instructions.
68 */
69volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
70volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
71
72uint32_t apic_id_mask = 0;
73
74static int apic_poll_errors(void);
75
76#ifdef LAPIC_VERBOSE
77static char *delmod_str[] = {
78 "Fixed",
79 "Lowest Priority",
80 "SMI",
81 "Reserved",
82 "NMI",
83 "INIT",
84 "STARTUP",
85 "ExtInt"
86};
87
88static char *destmod_str[] = {
89 "Physical",
90 "Logical"
91};
92
93static char *trigmod_str[] = {
94 "Edge",
95 "Level"
96};
97
98static char *mask_str[] = {
99 "Unmasked",
100 "Masked"
101};
102
103static char *delivs_str[] = {
104 "Idle",
105 "Send Pending"
106};
107
108static char *tm_mode_str[] = {
109 "One-shot",
110 "Periodic"
111};
112
113static char *intpol_str[] = {
114 "Polarity High",
115 "Polarity Low"
116};
117#endif /* LAPIC_VERBOSE */
118
119
120static void apic_spurious(int n, istate_t *istate);
121static void l_apic_timer_interrupt(int n, istate_t *istate);
122
123/** Initialize APIC on BSP. */
124void apic_init(void)
125{
126 io_apic_id_t idreg;
[623b49f1]127 unsigned int i;
[983cd374]128
129 exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
130
131 enable_irqs_function = io_apic_enable_irqs;
132 disable_irqs_function = io_apic_disable_irqs;
133 eoi_function = l_apic_eoi;
134
135 /*
136 * Configure interrupt routing.
137 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
138 * Other interrupts will be forwarded to the lowest priority CPU.
139 */
140 io_apic_disable_irqs(0xffff);
141 exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
142 for (i = 0; i < IRQ_COUNT; i++) {
143 int pin;
144
145 if ((pin = smp_irq_to_pin(i)) != -1) {
146 io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
147 }
148 }
149
150 /*
151 * Ensure that io_apic has unique ID.
152 */
153 idreg.value = io_apic_read(IOAPICID);
[f619ec11]154 if ((1 << idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
[983cd374]155 for (i = 0; i < APIC_ID_COUNT; i++) {
156 if (!((1<<i) & apic_id_mask)) {
157 idreg.apic_id = i;
158 io_apic_write(IOAPICID, idreg.value);
159 break;
160 }
161 }
162 }
163
164 /*
165 * Configure the BSP's lapic.
166 */
167 l_apic_init();
168
169 l_apic_debug();
170}
171
172/** APIC spurious interrupt handler.
173 *
174 * @param n Interrupt vector.
175 * @param istate Interrupted state.
176 */
177void apic_spurious(int n, istate_t *istate)
178{
179#ifdef CONFIG_DEBUG
180 printf("cpu%d: APIC spurious interrupt\n", CPU->id);
181#endif
182}
183
184/** Poll for APIC errors.
185 *
186 * Examine Error Status Register and report all errors found.
187 *
188 * @return 0 on error, 1 on success.
189 */
190int apic_poll_errors(void)
191{
192 esr_t esr;
193
194 esr.value = l_apic[ESR];
195
196 if (esr.send_checksum_error)
197 printf("Send Checksum Error\n");
198 if (esr.receive_checksum_error)
199 printf("Receive Checksum Error\n");
200 if (esr.send_accept_error)
201 printf("Send Accept Error\n");
202 if (esr.receive_accept_error)
203 printf("Receive Accept Error\n");
204 if (esr.send_illegal_vector)
205 printf("Send Illegal Vector\n");
206 if (esr.received_illegal_vector)
207 printf("Received Illegal Vector\n");
208 if (esr.illegal_register_address)
209 printf("Illegal Register Address\n");
210
211 return !esr.err_bitmap;
212}
213
214/** Send all CPUs excluding CPU IPI vector.
215 *
216 * @param vector Interrupt vector to be sent.
217 *
218 * @return 0 on failure, 1 on success.
219 */
220int l_apic_broadcast_custom_ipi(uint8_t vector)
221{
222 icr_t icr;
223
224 icr.lo = l_apic[ICRlo];
225 icr.delmod = DELMOD_FIXED;
226 icr.destmod = DESTMOD_LOGIC;
227 icr.level = LEVEL_ASSERT;
228 icr.shorthand = SHORTHAND_ALL_EXCL;
229 icr.trigger_mode = TRIGMOD_LEVEL;
230 icr.vector = vector;
231
232 l_apic[ICRlo] = icr.lo;
233
234 icr.lo = l_apic[ICRlo];
235 if (icr.delivs == DELIVS_PENDING) {
236#ifdef CONFIG_DEBUG
237 printf("IPI is pending.\n");
238#endif
239 }
240
241 return apic_poll_errors();
242}
243
244/** Universal Start-up Algorithm for bringing up the AP processors.
245 *
246 * @param apicid APIC ID of the processor to be brought up.
247 *
248 * @return 0 on failure, 1 on success.
249 */
250int l_apic_send_init_ipi(uint8_t apicid)
251{
252 icr_t icr;
253 int i;
254
255 /*
256 * Read the ICR register in and zero all non-reserved fields.
257 */
258 icr.lo = l_apic[ICRlo];
259 icr.hi = l_apic[ICRhi];
260
261 icr.delmod = DELMOD_INIT;
262 icr.destmod = DESTMOD_PHYS;
263 icr.level = LEVEL_ASSERT;
264 icr.trigger_mode = TRIGMOD_LEVEL;
265 icr.shorthand = SHORTHAND_NONE;
266 icr.vector = 0;
267 icr.dest = apicid;
268
269 l_apic[ICRhi] = icr.hi;
270 l_apic[ICRlo] = icr.lo;
271
272 /*
273 * According to MP Specification, 20us should be enough to
274 * deliver the IPI.
275 */
276 delay(20);
277
278 if (!apic_poll_errors())
279 return 0;
280
281 icr.lo = l_apic[ICRlo];
282 if (icr.delivs == DELIVS_PENDING) {
283#ifdef CONFIG_DEBUG
284 printf("IPI is pending.\n");
285#endif
286 }
287
288 icr.delmod = DELMOD_INIT;
289 icr.destmod = DESTMOD_PHYS;
290 icr.level = LEVEL_DEASSERT;
291 icr.shorthand = SHORTHAND_NONE;
292 icr.trigger_mode = TRIGMOD_LEVEL;
293 icr.vector = 0;
294 l_apic[ICRlo] = icr.lo;
295
296 /*
297 * Wait 10ms as MP Specification specifies.
298 */
299 delay(10000);
300
301 if (!is_82489DX_apic(l_apic[LAVR])) {
302 /*
303 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
304 */
[f619ec11]305 for (i = 0; i < 2; i++) {
[983cd374]306 icr.lo = l_apic[ICRlo];
307 icr.delmod = DELMOD_STARTUP;
308 icr.destmod = DESTMOD_PHYS;
309 icr.level = LEVEL_ASSERT;
310 icr.shorthand = SHORTHAND_NONE;
311 icr.trigger_mode = TRIGMOD_LEVEL;
312 l_apic[ICRlo] = icr.lo;
313 delay(200);
314 }
315 }
316
317 return apic_poll_errors();
318}
319
320/** Initialize Local APIC. */
321void l_apic_init(void)
322{
323 lvt_error_t error;
324 lvt_lint_t lint;
325 tpr_t tpr;
326 svr_t svr;
327 icr_t icr;
328 tdcr_t tdcr;
329 lvt_tm_t tm;
330 ldr_t ldr;
331 dfr_t dfr;
332 uint32_t t1, t2;
333
334 /* Initialize LVT Error register. */
335 error.value = l_apic[LVT_Err];
336 error.masked = true;
337 l_apic[LVT_Err] = error.value;
338
339 /* Initialize LVT LINT0 register. */
340 lint.value = l_apic[LVT_LINT0];
341 lint.masked = true;
342 l_apic[LVT_LINT0] = lint.value;
343
344 /* Initialize LVT LINT1 register. */
345 lint.value = l_apic[LVT_LINT1];
346 lint.masked = true;
347 l_apic[LVT_LINT1] = lint.value;
348
349 /* Task Priority Register initialization. */
350 tpr.value = l_apic[TPR];
351 tpr.pri_sc = 0;
352 tpr.pri = 0;
353 l_apic[TPR] = tpr.value;
354
355 /* Spurious-Interrupt Vector Register initialization. */
356 svr.value = l_apic[SVR];
357 svr.vector = VECTOR_APIC_SPUR;
358 svr.lapic_enabled = true;
359 svr.focus_checking = true;
360 l_apic[SVR] = svr.value;
361
362 if (CPU->arch.family >= 6)
363 enable_l_apic_in_msr();
364
365 /* Interrupt Command Register initialization. */
366 icr.lo = l_apic[ICRlo];
367 icr.delmod = DELMOD_INIT;
368 icr.destmod = DESTMOD_PHYS;
369 icr.level = LEVEL_DEASSERT;
370 icr.shorthand = SHORTHAND_ALL_INCL;
371 icr.trigger_mode = TRIGMOD_LEVEL;
372 l_apic[ICRlo] = icr.lo;
373
374 /* Timer Divide Configuration Register initialization. */
375 tdcr.value = l_apic[TDCR];
376 tdcr.div_value = DIVIDE_1;
377 l_apic[TDCR] = tdcr.value;
378
379 /* Program local timer. */
380 tm.value = l_apic[LVT_Tm];
381 tm.vector = VECTOR_CLK;
382 tm.mode = TIMER_PERIODIC;
383 tm.masked = false;
384 l_apic[LVT_Tm] = tm.value;
385
386 /*
387 * Measure and configure the timer to generate timer
388 * interrupt with period 1s/HZ seconds.
389 */
390 t1 = l_apic[CCRT];
391 l_apic[ICRT] = 0xffffffff;
392
393 while (l_apic[CCRT] == t1)
394 ;
395
396 t1 = l_apic[CCRT];
397 delay(1000000/HZ);
398 t2 = l_apic[CCRT];
399
400 l_apic[ICRT] = t1-t2;
401
402 /* Program Logical Destination Register. */
403 ldr.value = l_apic[LDR];
[f619ec11]404 if (CPU->id < sizeof(CPU->id) * 8) /* size in bits */
405 ldr.id = (1 << CPU->id);
[983cd374]406 l_apic[LDR] = ldr.value;
407
408 /* Program Destination Format Register for Flat mode. */
409 dfr.value = l_apic[DFR];
410 dfr.model = MODEL_FLAT;
411 l_apic[DFR] = dfr.value;
412}
413
414/** Local APIC End of Interrupt. */
415void l_apic_eoi(void)
416{
417 l_apic[EOI] = 0;
418}
419
420/** Dump content of Local APIC registers. */
421void l_apic_debug(void)
422{
423#ifdef LAPIC_VERBOSE
424 lvt_tm_t tm;
425 lvt_lint_t lint;
426 lvt_error_t error;
427
428 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
429
430 tm.value = l_apic[LVT_Tm];
431 printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
432 lint.value = l_apic[LVT_LINT0];
433 printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
434 lint.value = l_apic[LVT_LINT1];
435 printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
436 error.value = l_apic[LVT_Err];
437 printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
438#endif
439}
440
441/** Local APIC Timer Interrupt.
442 *
443 * @param n Interrupt vector number.
444 * @param istate Interrupted state.
445 */
446void l_apic_timer_interrupt(int n, istate_t *istate)
447{
448 l_apic_eoi();
449 clock();
450}
451
452/** Get Local APIC ID.
453 *
454 * @return Local APIC ID.
455 */
456uint8_t l_apic_id(void)
457{
458 l_apic_id_t idreg;
459
460 idreg.value = l_apic[L_APIC_ID];
461 return idreg.apic_id;
462}
463
464/** Read from IO APIC register.
465 *
466 * @param address IO APIC register address.
467 *
468 * @return Content of the addressed IO APIC register.
469 */
470uint32_t io_apic_read(uint8_t address)
471{
472 io_regsel_t regsel;
473
474 regsel.value = io_apic[IOREGSEL];
475 regsel.reg_addr = address;
476 io_apic[IOREGSEL] = regsel.value;
477 return io_apic[IOWIN];
478}
479
480/** Write to IO APIC register.
481 *
482 * @param address IO APIC register address.
483 * @param x Content to be written to the addressed IO APIC register.
484 */
485void io_apic_write(uint8_t address, uint32_t x)
486{
487 io_regsel_t regsel;
488
489 regsel.value = io_apic[IOREGSEL];
490 regsel.reg_addr = address;
491 io_apic[IOREGSEL] = regsel.value;
492 io_apic[IOWIN] = x;
493}
494
495/** Change some attributes of one item in I/O Redirection Table.
496 *
497 * @param pin IO APIC pin number.
498 * @param dest Interrupt destination address.
499 * @param v Interrupt vector to trigger.
500 * @param flags Flags.
501 */
[566f5e5c]502void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags)
[983cd374]503{
504 io_redirection_reg_t reg;
505 int dlvr = DELMOD_FIXED;
506
507 if (flags & LOPRI)
508 dlvr = DELMOD_LOWPRI;
509
[f619ec11]510 reg.lo = io_apic_read(IOREDTBL + pin * 2);
511 reg.hi = io_apic_read(IOREDTBL + pin * 2 + 1);
[983cd374]512
513 reg.dest = dest;
514 reg.destmod = DESTMOD_LOGIC;
515 reg.trigger_mode = TRIGMOD_EDGE;
516 reg.intpol = POLARITY_HIGH;
517 reg.delmod = dlvr;
518 reg.intvec = v;
519
[f619ec11]520 io_apic_write(IOREDTBL + pin * 2, reg.lo);
521 io_apic_write(IOREDTBL + pin * 2 + 1, reg.hi);
[983cd374]522}
523
524/** Mask IRQs in IO APIC.
525 *
526 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
527 */
528void io_apic_disable_irqs(uint16_t irqmask)
529{
530 io_redirection_reg_t reg;
[623b49f1]531 unsigned int i;
532 int pin;
[983cd374]533
[623b49f1]534 for (i = 0; i < 16; i++) {
535 if (irqmask & (1 << i)) {
[983cd374]536 /*
537 * Mask the signal input in IO APIC if there is a
538 * mapping for the respective IRQ number.
539 */
540 pin = smp_irq_to_pin(i);
541 if (pin != -1) {
[f619ec11]542 reg.lo = io_apic_read(IOREDTBL + pin * 2);
[983cd374]543 reg.masked = true;
544 io_apic_write(IOREDTBL + pin*2, reg.lo);
545 }
546
547 }
548 }
549}
550
551/** Unmask IRQs in IO APIC.
552 *
553 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
554 */
555void io_apic_enable_irqs(uint16_t irqmask)
556{
[623b49f1]557 unsigned int i;
558 int pin;
[983cd374]559 io_redirection_reg_t reg;
560
[623b49f1]561 for (i = 0; i < 16; i++) {
562 if (irqmask & (1 << i)) {
[983cd374]563 /*
564 * Unmask the signal input in IO APIC if there is a
565 * mapping for the respective IRQ number.
566 */
567 pin = smp_irq_to_pin(i);
568 if (pin != -1) {
[f619ec11]569 reg.lo = io_apic_read(IOREDTBL + pin * 2);
[983cd374]570 reg.masked = false;
571 io_apic_write(IOREDTBL + pin*2, reg.lo);
572 }
573
574 }
575 }
576}
577
578#endif /* CONFIG_SMP */
579
580/** @}
581 */
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