| 1 | /*
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| 2 | * Copyright (C) 2006 Martin Decky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup ia32xen_mm
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #ifndef KERN_ia32xen_PAGE_H_
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| 36 | #define KERN_ia32xen_PAGE_H_
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| 37 |
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| 38 | #include <arch/mm/frame.h>
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| 39 |
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| 40 | #define PAGE_WIDTH FRAME_WIDTH
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| 41 | #define PAGE_SIZE FRAME_SIZE
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| 42 |
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| 43 | #define PAGE_COLOR_BITS 0 /* dummy */
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| 44 |
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| 45 | #ifdef KERNEL
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| 46 |
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| 47 | #ifndef __ASM__
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| 48 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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| 49 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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| 50 | #else
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| 51 | # define KA2PA(x) ((x) - 0x80000000)
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| 52 | # define PA2KA(x) ((x) + 0x80000000)
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| 53 | #endif
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| 54 |
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| 55 | /*
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| 56 | * Implementation of generic 4-level page table interface.
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| 57 | * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
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| 58 | */
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| 59 | #define PTL0_ENTRIES_ARCH 1024
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| 60 | #define PTL1_ENTRIES_ARCH 0
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| 61 | #define PTL2_ENTRIES_ARCH 0
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| 62 | #define PTL3_ENTRIES_ARCH 1024
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| 63 |
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| 64 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
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| 65 | #define PTL1_INDEX_ARCH(vaddr) 0
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| 66 | #define PTL2_INDEX_ARCH(vaddr) 0
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| 67 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
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| 68 |
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| 69 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
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| 70 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
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| 71 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
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| 72 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
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| 73 |
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| 74 | #define SET_PTL0_ADDRESS_ARCH(ptl0) { \
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| 75 | mmuext_op_t mmu_ext; \
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| 76 | \
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| 77 | mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
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| 78 | mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
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| 79 | ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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| 80 | }
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| 81 |
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| 82 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) { \
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| 83 | mmuext_op_t mmu_ext; \
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| 84 | \
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| 85 | mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
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| 86 | mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
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| 87 | ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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| 88 | \
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| 89 | mmu_update_t update; \
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| 90 | \
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| 91 | update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
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| 92 | update.val = PA2MA(a); \
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| 93 | ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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| 94 | }
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| 95 |
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| 96 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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| 97 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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| 98 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) { \
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| 99 | mmu_update_t update; \
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| 100 | \
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| 101 | update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
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| 102 | update.val = PA2MA(a); \
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| 103 | ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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| 104 | }
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| 105 |
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| 106 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t)(i))
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| 107 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
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| 108 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
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| 109 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t)(i))
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| 110 |
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| 111 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t)(i), (x))
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| 112 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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| 113 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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| 114 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t)(i), (x))
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| 115 |
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| 116 | #define PTE_VALID_ARCH(p) (*((uint32_t *) (p)) != 0)
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| 117 | #define PTE_PRESENT_ARCH(p) ((p)->present != 0)
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| 118 | #define PTE_GET_FRAME_ARCH(p) ((p)->frame_address << FRAME_WIDTH)
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| 119 | #define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
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| 120 | #define PTE_EXECUTABLE_ARCH(p) 1
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| 121 |
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| 122 | #ifndef __ASM__
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| 123 |
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| 124 | #include <mm/page.h>
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| 125 | #include <arch/types.h>
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| 126 | #include <arch/mm/frame.h>
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| 127 | #include <typedefs.h>
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| 128 | #include <arch/hypercall.h>
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| 129 |
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| 130 | /* Page fault error codes. */
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| 131 |
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| 132 | /** When bit on this position is 0, the page fault was caused by a not-present page. */
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| 133 | #define PFERR_CODE_P (1 << 0)
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| 134 |
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| 135 | /** When bit on this position is 1, the page fault was caused by a write. */
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| 136 | #define PFERR_CODE_RW (1 << 1)
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| 137 |
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| 138 | /** When bit on this position is 1, the page fault was caused in user mode. */
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| 139 | #define PFERR_CODE_US (1 << 2)
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| 140 |
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| 141 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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| 142 | #define PFERR_CODE_RSVD (1 << 3)
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| 143 |
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| 144 | /** Page Table Entry. */
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| 145 | struct page_specifier {
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| 146 | unsigned present : 1;
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| 147 | unsigned writeable : 1;
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| 148 | unsigned uaccessible : 1;
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| 149 | unsigned page_write_through : 1;
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| 150 | unsigned page_cache_disable : 1;
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| 151 | unsigned accessed : 1;
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| 152 | unsigned dirty : 1;
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| 153 | unsigned pat : 1;
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| 154 | unsigned global : 1;
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| 155 | unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */
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| 156 | unsigned avl : 2;
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| 157 | unsigned frame_address : 20;
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| 158 | } __attribute__ ((packed));
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| 159 |
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| 160 | typedef struct {
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| 161 | uint64_t ptr; /**< Machine address of PTE */
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| 162 | union { /**< New contents of PTE */
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| 163 | uint64_t val;
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| 164 | pte_t pte;
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| 165 | };
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| 166 | } mmu_update_t;
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| 167 |
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| 168 | typedef struct {
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| 169 | unsigned int cmd;
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| 170 | union {
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| 171 | unsigned long mfn;
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| 172 | unsigned long linear_addr;
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| 173 | };
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| 174 | union {
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| 175 | unsigned int nr_ents;
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| 176 | void *vcpumask;
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| 177 | };
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| 178 | } mmuext_op_t;
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| 179 |
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| 180 | static inline int xen_update_va_mapping(const void *va, const pte_t pte, const unsigned int flags)
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| 181 | {
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| 182 | return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
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| 183 | }
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| 184 |
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| 185 | static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid)
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| 186 | {
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| 187 | return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
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| 188 | }
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| 189 |
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| 190 | static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid)
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| 191 | {
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| 192 | return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
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| 193 | }
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| 194 |
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| 195 | static inline int get_pt_flags(pte_t *pt, index_t i)
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| 196 | {
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| 197 | pte_t *p = &pt[i];
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| 198 |
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| 199 | return (
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| 200 | (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
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| 201 | (!p->present)<<PAGE_PRESENT_SHIFT |
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| 202 | p->uaccessible<<PAGE_USER_SHIFT |
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| 203 | 1<<PAGE_READ_SHIFT |
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| 204 | p->writeable<<PAGE_WRITE_SHIFT |
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| 205 | 1<<PAGE_EXEC_SHIFT |
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| 206 | p->global<<PAGE_GLOBAL_SHIFT
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| 207 | );
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| 208 | }
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| 209 |
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| 210 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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| 211 | {
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| 212 | pte_t p = pt[i];
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| 213 |
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| 214 | p.page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 215 | p.present = !(flags & PAGE_NOT_PRESENT);
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| 216 | p.uaccessible = (flags & PAGE_USER) != 0;
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| 217 | p.writeable = (flags & PAGE_WRITE) != 0;
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| 218 | p.global = (flags & PAGE_GLOBAL) != 0;
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| 219 |
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| 220 | /*
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| 221 | * Ensure that there is at least one bit set even if the present bit is cleared.
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| 222 | */
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| 223 | p.soft_valid = true;
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| 224 |
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| 225 | mmu_update_t update;
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| 226 |
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| 227 | update.ptr = PA2MA(KA2PA(&(pt[i])));
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| 228 | update.pte = p;
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| 229 | xen_mmu_update(&update, 1, NULL, DOMID_SELF);
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| 230 | }
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| 231 |
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| 232 | extern void page_arch_init(void);
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| 233 | extern void page_fault(int n, istate_t *istate);
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| 234 |
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| 235 | #endif /* __ASM__ */
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| 236 |
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| 237 | #endif /* KERNEL */
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| 238 |
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| 239 | #endif
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| 240 |
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| 241 | /** @}
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| 242 | */
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