| [983cd374] | 1 | /*
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| [df4ed85] | 2 | * Copyright (c) 2006 Martin Decky
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| [983cd374] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| [57ce359] | 29 | /** @addtogroup ia32xen_mm
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| [983cd374] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| [57ce359] | 35 | #ifndef KERN_ia32xen_PAGE_H_
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| 36 | #define KERN_ia32xen_PAGE_H_
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| [983cd374] | 37 |
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| 38 | #include <arch/mm/frame.h>
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| 39 |
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| 40 | #define PAGE_WIDTH FRAME_WIDTH
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| 41 | #define PAGE_SIZE FRAME_SIZE
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| 42 |
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| [d0485c6] | 43 | #define PAGE_COLOR_BITS 0 /* dummy */
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| 44 |
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| [983cd374] | 45 | #ifdef KERNEL
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| 46 |
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| 47 | #ifndef __ASM__
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| 48 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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| 49 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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| 50 | #else
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| 51 | # define KA2PA(x) ((x) - 0x80000000)
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| 52 | # define PA2KA(x) ((x) + 0x80000000)
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| 53 | #endif
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| 54 |
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| 55 | /*
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| 56 | * Implementation of generic 4-level page table interface.
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| 57 | * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
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| 58 | */
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| [c03ee1c] | 59 |
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| 60 | /* Number of entries in each level. */
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| [983cd374] | 61 | #define PTL0_ENTRIES_ARCH 1024
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| 62 | #define PTL1_ENTRIES_ARCH 0
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| 63 | #define PTL2_ENTRIES_ARCH 0
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| 64 | #define PTL3_ENTRIES_ARCH 1024
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| 65 |
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| [c03ee1c] | 66 | /* Page table size for each level. */
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| 67 | #define PTL0_SIZE_ARCH ONE_FRAME
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| 68 | #define PTL1_SIZE_ARCH 0
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| 69 | #define PTL2_SIZE_ARCH 0
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| 70 | #define PTL3_SIZE_ARCH ONE_FRAME
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| [6b781c0] | 71 |
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| [c03ee1c] | 72 | /* Macros calculating indices into page tables in each level. */
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| [c049309] | 73 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
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| [983cd374] | 74 | #define PTL1_INDEX_ARCH(vaddr) 0
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| 75 | #define PTL2_INDEX_ARCH(vaddr) 0
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| [c049309] | 76 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
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| [983cd374] | 77 |
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| [c03ee1c] | 78 | /* Get PTE address accessors for each level. */
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| 79 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 80 | ((pte_t *) MA2PA((((pte_t *) (ptl0))[(i)].frame_address) << 12))
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| 81 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 82 | (ptl1)
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| 83 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 84 | (ptl2)
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| 85 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 86 | ((uintptr_t) MA2PA((((pte_t *) (ptl3))[(i)].frame_address) << 12))
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| 87 |
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| 88 | /* Set PTE address accessors for each level. */
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| 89 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \
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| 90 | { \
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| [c049309] | 91 | mmuext_op_t mmu_ext; \
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| [e12ccc5] | 92 | \
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| [c049309] | 93 | mmu_ext.cmd = MMUEXT_NEW_BASEPTR; \
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| [e12ccc5] | 94 | mmu_ext.mfn = ADDR2PFN(PA2MA(ptl0)); \
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| [8cd140f2] | 95 | ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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| [c049309] | 96 | }
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| [e12ccc5] | 97 |
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| [c03ee1c] | 98 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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| 99 | { \
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| [8cd140f2] | 100 | mmuext_op_t mmu_ext; \
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| 101 | \
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| 102 | mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; \
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| 103 | mmu_ext.mfn = ADDR2PFN(PA2MA(a)); \
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| 104 | ASSERT(xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) == 0); \
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| 105 | \
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| [c049309] | 106 | mmu_update_t update; \
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| [e12ccc5] | 107 | \
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| [c049309] | 108 | update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl0))[(i)])); \
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| [8cd140f2] | 109 | update.val = PA2MA(a); \
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| 110 | ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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| [c049309] | 111 | }
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| [8cd140f2] | 112 |
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| [983cd374] | 113 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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| 114 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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| [c03ee1c] | 115 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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| 116 | { \
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| [8cd140f2] | 117 | mmu_update_t update; \
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| 118 | \
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| 119 | update.ptr = PA2MA(KA2PA(&((pte_t *) (ptl3))[(i)])); \
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| 120 | update.val = PA2MA(a); \
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| 121 | ASSERT(xen_mmu_update(&update, 1, NULL, DOMID_SELF) == 0); \
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| 122 | }
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| [983cd374] | 123 |
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| [c03ee1c] | 124 | /* Get PTE flags accessors for each level. */
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| 125 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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| 126 | get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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| 127 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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| 128 | PAGE_PRESENT
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| 129 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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| 130 | PAGE_PRESENT
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| 131 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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| 132 | get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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| 133 |
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| 134 | /* Set PTE flags accessors for each level. */
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| 135 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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| 136 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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| [983cd374] | 137 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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| 138 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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| [c03ee1c] | 139 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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| 140 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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| 141 |
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| 142 | /* Query macros for the last level. */
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| 143 | #define PTE_VALID_ARCH(p) \
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| 144 | (*((uint32_t *) (p)) != 0)
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| 145 | #define PTE_PRESENT_ARCH(p) \
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| 146 | ((p)->present != 0)
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| 147 | #define PTE_GET_FRAME_ARCH(p) \
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| 148 | ((p)->frame_address << FRAME_WIDTH)
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| 149 | #define PTE_WRITABLE_ARCH(p) \
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| 150 | ((p)->writeable != 0)
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| 151 | #define PTE_EXECUTABLE_ARCH(p) \
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| 152 | 1
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| [983cd374] | 153 |
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| 154 | #ifndef __ASM__
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| 155 |
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| [b3f8fb7] | 156 | #include <mm/mm.h>
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| [e12ccc5] | 157 | #include <arch/hypercall.h>
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| [b3f8fb7] | 158 | #include <arch/interrupt.h>
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| [983cd374] | 159 |
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| 160 | /* Page fault error codes. */
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| 161 |
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| [c03ee1c] | 162 | /** When bit on this position is 0, the page fault was caused by a not-present
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| 163 | * page.
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| 164 | */
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| [c049309] | 165 | #define PFERR_CODE_P (1 << 0)
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| [983cd374] | 166 |
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| 167 | /** When bit on this position is 1, the page fault was caused by a write. */
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| [c049309] | 168 | #define PFERR_CODE_RW (1 << 1)
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| [983cd374] | 169 |
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| 170 | /** When bit on this position is 1, the page fault was caused in user mode. */
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| [c049309] | 171 | #define PFERR_CODE_US (1 << 2)
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| [983cd374] | 172 |
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| 173 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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| [c049309] | 174 | #define PFERR_CODE_RSVD (1 << 3)
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| [983cd374] | 175 |
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| [e12ccc5] | 176 | typedef struct {
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| 177 | uint64_t ptr; /**< Machine address of PTE */
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| 178 | union { /**< New contents of PTE */
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| 179 | uint64_t val;
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| 180 | pte_t pte;
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| 181 | };
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| 182 | } mmu_update_t;
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| 183 |
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| 184 | typedef struct {
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| 185 | unsigned int cmd;
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| 186 | union {
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| 187 | unsigned long mfn;
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| 188 | unsigned long linear_addr;
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| 189 | };
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| 190 | union {
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| 191 | unsigned int nr_ents;
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| 192 | void *vcpumask;
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| 193 | };
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| 194 | } mmuext_op_t;
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| 195 |
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| [c03ee1c] | 196 | static inline int xen_update_va_mapping(const void *va, const pte_t pte,
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| 197 | const unsigned int flags)
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| [e12ccc5] | 198 | {
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| 199 | return hypercall4(XEN_UPDATE_VA_MAPPING, va, pte, 0, flags);
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| 200 | }
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| 201 |
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| [c03ee1c] | 202 | static inline int xen_mmu_update(const mmu_update_t *req,
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| 203 | const unsigned int count, unsigned int *success_count, domid_t domid)
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| [e12ccc5] | 204 | {
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| 205 | return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid);
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| 206 | }
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| 207 |
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| [c03ee1c] | 208 | static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count,
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| 209 | unsigned int *success_count, domid_t domid)
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| [e12ccc5] | 210 | {
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| 211 | return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid);
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| 212 | }
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| 213 |
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| [983cd374] | 214 | static inline int get_pt_flags(pte_t *pt, index_t i)
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| 215 | {
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| 216 | pte_t *p = &pt[i];
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| 217 |
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| [c03ee1c] | 218 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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| 219 | (!p->present) << PAGE_PRESENT_SHIFT |
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| 220 | p->uaccessible << PAGE_USER_SHIFT |
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| 221 | 1 << PAGE_READ_SHIFT |
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| 222 | p->writeable << PAGE_WRITE_SHIFT |
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| 223 | 1 << PAGE_EXEC_SHIFT |
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| 224 | p->global << PAGE_GLOBAL_SHIFT);
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| [983cd374] | 225 | }
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| 226 |
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| 227 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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| 228 | {
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| [8cd140f2] | 229 | pte_t p = pt[i];
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| [983cd374] | 230 |
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| [8cd140f2] | 231 | p.page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 232 | p.present = !(flags & PAGE_NOT_PRESENT);
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| 233 | p.uaccessible = (flags & PAGE_USER) != 0;
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| 234 | p.writeable = (flags & PAGE_WRITE) != 0;
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| 235 | p.global = (flags & PAGE_GLOBAL) != 0;
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| [983cd374] | 236 |
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| 237 | /*
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| 238 | * Ensure that there is at least one bit set even if the present bit is cleared.
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| 239 | */
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| [8cd140f2] | 240 | p.soft_valid = true;
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| 241 |
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| 242 | mmu_update_t update;
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| 243 |
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| 244 | update.ptr = PA2MA(KA2PA(&(pt[i])));
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| 245 | update.pte = p;
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| 246 | xen_mmu_update(&update, 1, NULL, DOMID_SELF);
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| [983cd374] | 247 | }
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| 248 |
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| 249 | extern void page_arch_init(void);
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| 250 | extern void page_fault(int n, istate_t *istate);
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| 251 |
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| 252 | #endif /* __ASM__ */
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| 253 |
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| 254 | #endif /* KERNEL */
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| 255 |
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| 256 | #endif
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| 257 |
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| 258 | /** @}
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| 259 | */
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