source: mainline/kernel/arch/ia32/src/smp/smp.c@ d71331b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d71331b was 49e6c6b4, checked in by Adam Hraska <adam.hraska+hos@…>, 13 years ago

ipi: Added support for unicast IPI on amd64, ia32.

  • Property mode set to 100644
File size: 5.4 KB
RevLine 
[ed0dd65]1/*
[4bb31f7]2 * Copyright (c) 2008 Jakub Jermar
[ed0dd65]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[99d6fd0]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed0dd65]35#include <smp/smp.h>
[a26ddd1]36#include <arch/smp/smp.h>
37#include <arch/smp/mps.h>
38#include <arch/smp/ap.h>
[66def8d]39#include <arch/boot/boot.h>
[e16e036a]40#include <genarch/acpi/acpi.h>
41#include <genarch/acpi/madt.h>
[ed0dd65]42#include <config.h>
[a26ddd1]43#include <synch/waitq.h>
44#include <arch/pm.h>
45#include <func.h>
46#include <panic.h>
47#include <debug.h>
48#include <arch/asm.h>
49#include <mm/page.h>
[d4673296]50#include <mm/frame.h>
51#include <mm/km.h>
[085d973]52#include <mm/slab.h>
[fc1e4f6]53#include <mm/as.h>
[9c0a9b3]54#include <print.h>
55#include <memstr.h>
[80d31883]56#include <arch/drivers/i8259.h>
[49e6c6b4]57#include <cpu.h>
[ed0dd65]58
[5f85c91]59#ifdef CONFIG_SMP
[ed0dd65]60
[a26ddd1]61static struct smp_config_operations *ops = NULL;
62
[ed0dd65]63void smp_init(void)
64{
65 if (acpi_madt) {
66 acpi_madt_parse();
[232e3ec7]67 ops = &madt_config_operations;
[ed0dd65]68 }
[fe32163]69
[a26ddd1]70 if (config.cpu_count == 1) {
[ed0dd65]71 mps_init();
[a26ddd1]72 ops = &mps_config_operations;
73 }
[fe32163]74
[e3ce39b]75 if (config.cpu_count > 1) {
[adec5b45]76 l_apic = (uint32_t *) km_map((uintptr_t) l_apic, PAGE_SIZE,
77 PAGE_WRITE | PAGE_NOT_CACHEABLE);
78 io_apic = (uint32_t *) km_map((uintptr_t) io_apic, PAGE_SIZE,
79 PAGE_WRITE | PAGE_NOT_CACHEABLE);
[7cb567cd]80 }
[ed0dd65]81}
82
[49e6c6b4]83static void cpu_arch_id_init(void)
84{
85 ASSERT(ops != NULL);
86 ASSERT(cpus != NULL);
87
88 for (unsigned int i = 0; i < config.cpu_count; ++i) {
89 cpus[i].arch.id = ops->cpu_apic_id(i);
90 }
91}
92
[a26ddd1]93/*
94 * Kernel thread for bringing up application processors. It becomes clear
95 * that we need an arrangement like this (AP's being initialized by a kernel
96 * thread), for a thread has its dedicated stack. (The stack used during the
97 * BSP initialization (prior the very first call to scheduler()) will be used
98 * as an initialization stack for each AP.)
99 */
[7f043c0]100void kmp(void *arg __attribute__((unused)))
[a26ddd1]101{
[c27c988]102 unsigned int i;
[6401f79]103
[a26ddd1]104 ASSERT(ops != NULL);
[49e6c6b4]105
106 /*
107 * SMP initialized, cpus array allocated. Assign each CPU its
108 * physical APIC ID.
109 */
110 cpu_arch_id_init();
[fe32163]111
[a26ddd1]112 /*
113 * We need to access data in frame 0.
114 * We boldly make use of kernel address space mapping.
115 */
[fe32163]116
[a26ddd1]117 /*
118 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
119 */
[4bb31f7]120 *((uint16_t *) (PA2KA(0x467 + 0))) =
[fe32163]121 (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */
122 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */
[a26ddd1]123
124 /*
125 * Save 0xa to address 0xf of the CMOS RAM.
126 * BIOS will not do the POST after the INIT signal.
127 */
[fe32163]128 pio_write_8((ioport8_t *) 0x70, 0xf);
129 pio_write_8((ioport8_t *) 0x71, 0xa);
130
[a26ddd1]131 pic_disable_irqs(0xffff);
132 apic_init();
[7f043c0]133
[fe32163]134 for (i = 0; i < config.cpu_count; i++) {
[a26ddd1]135 /*
136 * Skip processors marked unusable.
137 */
138 if (!ops->cpu_enabled(i))
139 continue;
[fe32163]140
[a26ddd1]141 /*
142 * The bootstrap processor is already up.
143 */
144 if (ops->cpu_bootstrap(i))
145 continue;
[fe32163]146
[99718a2e]147 if (ops->cpu_apic_id(i) == bsp_l_apic) {
148 printf("kmp: bad processor entry #%u, will not send IPI "
149 "to myself\n", i);
[a26ddd1]150 continue;
151 }
152
153 /*
154 * Prepare new GDT for CPU in question.
155 */
[5f0f29ce]156
157 /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
158 * it needs to be replaced by a generic fuctionality of
159 * the memory subsystem
160 */
[fe32163]161 descriptor_t *gdt_new =
162 (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t),
163 FRAME_ATOMIC);
[4bb31f7]164 if (!gdt_new)
[f651e80]165 panic("Cannot allocate memory for GDT.");
[fe32163]166
[99d6fd0]167 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t));
168 memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0);
169 protected_ap_gdtr.limit = GDT_ITEMS * sizeof(descriptor_t);
[7f1c620]170 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
171 gdtr.base = (uintptr_t) gdt_new;
[fe32163]172
[a26ddd1]173 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
174 /*
[c0b45fa]175 * There may be just one AP being initialized at
[a26ddd1]176 * the time. After it comes completely up, it is
177 * supposed to wake us up.
[c0b45fa]178 */
[4bb31f7]179 if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
180 SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
181 printf("%s: waiting for cpu%u (APIC ID = %d) "
[fe32163]182 "timed out\n", __FUNCTION__, i,
[4bb31f7]183 ops->cpu_apic_id(i));
[7f043c0]184 }
[c0b45fa]185 } else
[4bb31f7]186 printf("INIT IPI for l_apic%d failed\n",
187 ops->cpu_apic_id(i));
[a26ddd1]188 }
189}
[ed0dd65]190
[623b49f1]191int smp_irq_to_pin(unsigned int irq)
[a83a802]192{
193 ASSERT(ops != NULL);
194 return ops->irq_to_pin(irq);
195}
196
[5f85c91]197#endif /* CONFIG_SMP */
[b45c443]198
[06e1e95]199/** @}
[b45c443]200 */
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