[ed0dd65] | 1 | /*
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[4bb31f7] | 2 | * Copyright (c) 2008 Jakub Jermar
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[ed0dd65] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[99d6fd0] | 29 | /** @addtogroup ia32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[ed0dd65] | 35 | #include <smp/smp.h>
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[a26ddd1] | 36 | #include <arch/smp/smp.h>
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| 37 | #include <arch/smp/mps.h>
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| 38 | #include <arch/smp/ap.h>
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[66def8d] | 39 | #include <arch/boot/boot.h>
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[e16e036a] | 40 | #include <genarch/acpi/acpi.h>
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| 41 | #include <genarch/acpi/madt.h>
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[ed0dd65] | 42 | #include <config.h>
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[a26ddd1] | 43 | #include <synch/waitq.h>
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| 44 | #include <arch/pm.h>
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| 45 | #include <func.h>
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| 46 | #include <panic.h>
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| 47 | #include <debug.h>
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| 48 | #include <arch/asm.h>
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| 49 | #include <mm/page.h>
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[d4673296] | 50 | #include <mm/frame.h>
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| 51 | #include <mm/km.h>
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[085d973] | 52 | #include <mm/slab.h>
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[fc1e4f6] | 53 | #include <mm/as.h>
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[9c0a9b3] | 54 | #include <print.h>
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| 55 | #include <memstr.h>
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[80d31883] | 56 | #include <arch/drivers/i8259.h>
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[49e6c6b4] | 57 | #include <cpu.h>
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[ed0dd65] | 58 |
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[5f85c91] | 59 | #ifdef CONFIG_SMP
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[ed0dd65] | 60 |
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[a26ddd1] | 61 | static struct smp_config_operations *ops = NULL;
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| 62 |
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[ed0dd65] | 63 | void smp_init(void)
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| 64 | {
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| 65 | if (acpi_madt) {
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| 66 | acpi_madt_parse();
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[232e3ec7] | 67 | ops = &madt_config_operations;
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[ed0dd65] | 68 | }
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[fe32163] | 69 |
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[a26ddd1] | 70 | if (config.cpu_count == 1) {
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[ed0dd65] | 71 | mps_init();
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[a26ddd1] | 72 | ops = &mps_config_operations;
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| 73 | }
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[fe32163] | 74 |
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[e3ce39b] | 75 | if (config.cpu_count > 1) {
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[adec5b45] | 76 | l_apic = (uint32_t *) km_map((uintptr_t) l_apic, PAGE_SIZE,
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| 77 | PAGE_WRITE | PAGE_NOT_CACHEABLE);
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| 78 | io_apic = (uint32_t *) km_map((uintptr_t) io_apic, PAGE_SIZE,
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| 79 | PAGE_WRITE | PAGE_NOT_CACHEABLE);
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[7cb567cd] | 80 | }
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[ed0dd65] | 81 | }
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| 82 |
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[49e6c6b4] | 83 | static void cpu_arch_id_init(void)
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| 84 | {
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| 85 | ASSERT(ops != NULL);
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| 86 | ASSERT(cpus != NULL);
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| 87 |
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| 88 | for (unsigned int i = 0; i < config.cpu_count; ++i) {
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| 89 | cpus[i].arch.id = ops->cpu_apic_id(i);
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| 90 | }
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| 91 | }
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| 92 |
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[a26ddd1] | 93 | /*
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| 94 | * Kernel thread for bringing up application processors. It becomes clear
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| 95 | * that we need an arrangement like this (AP's being initialized by a kernel
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| 96 | * thread), for a thread has its dedicated stack. (The stack used during the
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| 97 | * BSP initialization (prior the very first call to scheduler()) will be used
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| 98 | * as an initialization stack for each AP.)
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| 99 | */
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[7f043c0] | 100 | void kmp(void *arg __attribute__((unused)))
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[a26ddd1] | 101 | {
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[c27c988] | 102 | unsigned int i;
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[6401f79] | 103 |
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[a26ddd1] | 104 | ASSERT(ops != NULL);
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[49e6c6b4] | 105 |
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| 106 | /*
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| 107 | * SMP initialized, cpus array allocated. Assign each CPU its
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| 108 | * physical APIC ID.
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| 109 | */
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| 110 | cpu_arch_id_init();
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[fe32163] | 111 |
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[a26ddd1] | 112 | /*
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| 113 | * We need to access data in frame 0.
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| 114 | * We boldly make use of kernel address space mapping.
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| 115 | */
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[fe32163] | 116 |
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[a26ddd1] | 117 | /*
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| 118 | * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
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| 119 | */
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[4bb31f7] | 120 | *((uint16_t *) (PA2KA(0x467 + 0))) =
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[fe32163] | 121 | (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */
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| 122 | *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */
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[a26ddd1] | 123 |
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| 124 | /*
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| 125 | * Save 0xa to address 0xf of the CMOS RAM.
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| 126 | * BIOS will not do the POST after the INIT signal.
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| 127 | */
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[fe32163] | 128 | pio_write_8((ioport8_t *) 0x70, 0xf);
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| 129 | pio_write_8((ioport8_t *) 0x71, 0xa);
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| 130 |
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[a26ddd1] | 131 | pic_disable_irqs(0xffff);
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| 132 | apic_init();
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[7f043c0] | 133 |
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[fe32163] | 134 | for (i = 0; i < config.cpu_count; i++) {
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[a26ddd1] | 135 | /*
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| 136 | * Skip processors marked unusable.
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| 137 | */
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| 138 | if (!ops->cpu_enabled(i))
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| 139 | continue;
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[fe32163] | 140 |
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[a26ddd1] | 141 | /*
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| 142 | * The bootstrap processor is already up.
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| 143 | */
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| 144 | if (ops->cpu_bootstrap(i))
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| 145 | continue;
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[fe32163] | 146 |
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[99718a2e] | 147 | if (ops->cpu_apic_id(i) == bsp_l_apic) {
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| 148 | printf("kmp: bad processor entry #%u, will not send IPI "
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| 149 | "to myself\n", i);
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[a26ddd1] | 150 | continue;
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| 151 | }
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| 152 |
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| 153 | /*
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| 154 | * Prepare new GDT for CPU in question.
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| 155 | */
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[5f0f29ce] | 156 |
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| 157 | /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
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| 158 | * it needs to be replaced by a generic fuctionality of
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| 159 | * the memory subsystem
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| 160 | */
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[fe32163] | 161 | descriptor_t *gdt_new =
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| 162 | (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t),
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| 163 | FRAME_ATOMIC);
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[4bb31f7] | 164 | if (!gdt_new)
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[f651e80] | 165 | panic("Cannot allocate memory for GDT.");
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[fe32163] | 166 |
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[99d6fd0] | 167 | memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t));
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| 168 | memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0);
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| 169 | protected_ap_gdtr.limit = GDT_ITEMS * sizeof(descriptor_t);
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[7f1c620] | 170 | protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
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| 171 | gdtr.base = (uintptr_t) gdt_new;
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[fe32163] | 172 |
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[a26ddd1] | 173 | if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
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| 174 | /*
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[c0b45fa] | 175 | * There may be just one AP being initialized at
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[a26ddd1] | 176 | * the time. After it comes completely up, it is
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| 177 | * supposed to wake us up.
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[c0b45fa] | 178 | */
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[4bb31f7] | 179 | if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
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| 180 | SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
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| 181 | printf("%s: waiting for cpu%u (APIC ID = %d) "
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[fe32163] | 182 | "timed out\n", __FUNCTION__, i,
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[4bb31f7] | 183 | ops->cpu_apic_id(i));
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[7f043c0] | 184 | }
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[c0b45fa] | 185 | } else
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[4bb31f7] | 186 | printf("INIT IPI for l_apic%d failed\n",
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| 187 | ops->cpu_apic_id(i));
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[a26ddd1] | 188 | }
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| 189 | }
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[ed0dd65] | 190 |
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[623b49f1] | 191 | int smp_irq_to_pin(unsigned int irq)
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[a83a802] | 192 | {
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| 193 | ASSERT(ops != NULL);
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| 194 | return ops->irq_to_pin(irq);
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| 195 | }
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| 196 |
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[5f85c91] | 197 | #endif /* CONFIG_SMP */
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[b45c443] | 198 |
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[06e1e95] | 199 | /** @}
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[b45c443] | 200 | */
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