source: mainline/kernel/arch/ia32/src/smp/smp.c@ cb15135a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cb15135a was 99718a2e, checked in by Martin Decky <martin@…>, 15 years ago

improve code readability

  • Property mode set to 100644
File size: 5.0 KB
RevLine 
[ed0dd65]1/*
[4bb31f7]2 * Copyright (c) 2008 Jakub Jermar
[ed0dd65]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[99d6fd0]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed0dd65]35#include <smp/smp.h>
[a26ddd1]36#include <arch/smp/smp.h>
37#include <arch/smp/mps.h>
38#include <arch/smp/ap.h>
[66def8d]39#include <arch/boot/boot.h>
[e16e036a]40#include <genarch/acpi/acpi.h>
41#include <genarch/acpi/madt.h>
[ed0dd65]42#include <config.h>
[a26ddd1]43#include <synch/waitq.h>
[6153749]44#include <synch/synch.h>
[a26ddd1]45#include <arch/pm.h>
46#include <func.h>
47#include <panic.h>
48#include <debug.h>
49#include <arch/asm.h>
50#include <mm/frame.h>
51#include <mm/page.h>
[085d973]52#include <mm/slab.h>
[fc1e4f6]53#include <mm/as.h>
[9c0a9b3]54#include <print.h>
55#include <memstr.h>
[80d31883]56#include <arch/drivers/i8259.h>
[ed0dd65]57
[5f85c91]58#ifdef CONFIG_SMP
[ed0dd65]59
[a26ddd1]60static struct smp_config_operations *ops = NULL;
61
[ed0dd65]62void smp_init(void)
63{
64 if (acpi_madt) {
65 acpi_madt_parse();
[232e3ec7]66 ops = &madt_config_operations;
[ed0dd65]67 }
[fe32163]68
[a26ddd1]69 if (config.cpu_count == 1) {
[ed0dd65]70 mps_init();
[a26ddd1]71 ops = &mps_config_operations;
72 }
[fe32163]73
[e3ce39b]74 if (config.cpu_count > 1) {
[0c3e63f]75 l_apic = (uint32_t *) hw_map((uintptr_t) l_apic, PAGE_SIZE);
76 io_apic = (uint32_t *) hw_map((uintptr_t) io_apic, PAGE_SIZE);
[7cb567cd]77 }
[ed0dd65]78}
79
[a26ddd1]80/*
81 * Kernel thread for bringing up application processors. It becomes clear
82 * that we need an arrangement like this (AP's being initialized by a kernel
83 * thread), for a thread has its dedicated stack. (The stack used during the
84 * BSP initialization (prior the very first call to scheduler()) will be used
85 * as an initialization stack for each AP.)
86 */
[7f043c0]87void kmp(void *arg __attribute__((unused)))
[a26ddd1]88{
[c27c988]89 unsigned int i;
[6401f79]90
[a26ddd1]91 ASSERT(ops != NULL);
[fe32163]92
[a26ddd1]93 /*
94 * We need to access data in frame 0.
95 * We boldly make use of kernel address space mapping.
96 */
[fe32163]97
[a26ddd1]98 /*
99 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
100 */
[4bb31f7]101 *((uint16_t *) (PA2KA(0x467 + 0))) =
[fe32163]102 (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */
103 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */
[a26ddd1]104
105 /*
106 * Save 0xa to address 0xf of the CMOS RAM.
107 * BIOS will not do the POST after the INIT signal.
108 */
[fe32163]109 pio_write_8((ioport8_t *) 0x70, 0xf);
110 pio_write_8((ioport8_t *) 0x71, 0xa);
111
[a26ddd1]112 pic_disable_irqs(0xffff);
113 apic_init();
[7f043c0]114
[fe32163]115 for (i = 0; i < config.cpu_count; i++) {
[a26ddd1]116 /*
117 * Skip processors marked unusable.
118 */
119 if (!ops->cpu_enabled(i))
120 continue;
[fe32163]121
[a26ddd1]122 /*
123 * The bootstrap processor is already up.
124 */
125 if (ops->cpu_bootstrap(i))
126 continue;
[fe32163]127
[99718a2e]128 if (ops->cpu_apic_id(i) == bsp_l_apic) {
129 printf("kmp: bad processor entry #%u, will not send IPI "
130 "to myself\n", i);
[a26ddd1]131 continue;
132 }
133
134 /*
135 * Prepare new GDT for CPU in question.
136 */
[5f0f29ce]137
138 /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
139 * it needs to be replaced by a generic fuctionality of
140 * the memory subsystem
141 */
[fe32163]142 descriptor_t *gdt_new =
143 (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t),
144 FRAME_ATOMIC);
[4bb31f7]145 if (!gdt_new)
[f651e80]146 panic("Cannot allocate memory for GDT.");
[fe32163]147
[99d6fd0]148 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t));
149 memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0);
150 protected_ap_gdtr.limit = GDT_ITEMS * sizeof(descriptor_t);
[7f1c620]151 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
152 gdtr.base = (uintptr_t) gdt_new;
[fe32163]153
[a26ddd1]154 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
155 /*
[c0b45fa]156 * There may be just one AP being initialized at
[a26ddd1]157 * the time. After it comes completely up, it is
158 * supposed to wake us up.
[c0b45fa]159 */
[4bb31f7]160 if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
161 SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
162 printf("%s: waiting for cpu%u (APIC ID = %d) "
[fe32163]163 "timed out\n", __FUNCTION__, i,
[4bb31f7]164 ops->cpu_apic_id(i));
[7f043c0]165 }
[c0b45fa]166 } else
[4bb31f7]167 printf("INIT IPI for l_apic%d failed\n",
168 ops->cpu_apic_id(i));
[a26ddd1]169 }
170}
[ed0dd65]171
[623b49f1]172int smp_irq_to_pin(unsigned int irq)
[a83a802]173{
174 ASSERT(ops != NULL);
175 return ops->irq_to_pin(irq);
176}
177
[5f85c91]178#endif /* CONFIG_SMP */
[b45c443]179
[06e1e95]180/** @}
[b45c443]181 */
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