source: mainline/kernel/arch/ia32/src/smp/smp.c@ c19aa612

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c19aa612 was fe32163, checked in by Martin Decky <martin@…>, 15 years ago

improve support for inactive CPUs
major revision of MADT and MPS parsing code
limit the number of active CPUs on ia32 and amd64 to 8 (actually the APIC ID of all active CPUs must be in the range 0 .. 7 to avoid tripping on an assertion in APIC code)
fix off-by-one bug in MADT parsing code (missing the last entry)

  • Property mode set to 100644
File size: 5.7 KB
RevLine 
[ed0dd65]1/*
[4bb31f7]2 * Copyright (c) 2008 Jakub Jermar
[ed0dd65]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[99d6fd0]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed0dd65]35#include <smp/smp.h>
[a26ddd1]36#include <arch/smp/smp.h>
37#include <arch/smp/mps.h>
38#include <arch/smp/ap.h>
[66def8d]39#include <arch/boot/boot.h>
[e16e036a]40#include <genarch/acpi/acpi.h>
41#include <genarch/acpi/madt.h>
[ed0dd65]42#include <config.h>
[a26ddd1]43#include <synch/waitq.h>
[6153749]44#include <synch/synch.h>
[a26ddd1]45#include <arch/pm.h>
46#include <func.h>
47#include <panic.h>
48#include <debug.h>
49#include <arch/asm.h>
50#include <mm/frame.h>
51#include <mm/page.h>
[085d973]52#include <mm/slab.h>
[fc1e4f6]53#include <mm/as.h>
[9c0a9b3]54#include <print.h>
55#include <memstr.h>
[80d31883]56#include <arch/drivers/i8259.h>
[ed0dd65]57
[5f85c91]58#ifdef CONFIG_SMP
[ed0dd65]59
[a26ddd1]60static struct smp_config_operations *ops = NULL;
61
[ed0dd65]62void smp_init(void)
63{
[fe32163]64 uintptr_t l_apic_address;
65 uintptr_t io_apic_address;
66
[ed0dd65]67 if (acpi_madt) {
68 acpi_madt_parse();
[232e3ec7]69 ops = &madt_config_operations;
[ed0dd65]70 }
[fe32163]71
[a26ddd1]72 if (config.cpu_count == 1) {
[ed0dd65]73 mps_init();
[a26ddd1]74 ops = &mps_config_operations;
75 }
[fe32163]76
[4bb31f7]77 l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME,
78 FRAME_ATOMIC | FRAME_KA);
[e45f81a]79 if (!l_apic_address)
[f651e80]80 panic("Cannot allocate address for l_apic.");
[fe32163]81
[4bb31f7]82 io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME,
83 FRAME_ATOMIC | FRAME_KA);
[e45f81a]84 if (!io_apic_address)
[f651e80]85 panic("Cannot allocate address for io_apic.");
[fe32163]86
[e3ce39b]87 if (config.cpu_count > 1) {
88 page_table_lock(AS_KERNEL, true);
[4bb31f7]89 page_mapping_insert(AS_KERNEL, l_apic_address,
90 (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE);
91 page_mapping_insert(AS_KERNEL, io_apic_address,
92 (uintptr_t) io_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE);
[e3ce39b]93 page_table_unlock(AS_KERNEL, true);
[fe32163]94
[7f1c620]95 l_apic = (uint32_t *) l_apic_address;
96 io_apic = (uint32_t *) io_apic_address;
[7cb567cd]97 }
[ed0dd65]98}
99
[a26ddd1]100/*
101 * Kernel thread for bringing up application processors. It becomes clear
102 * that we need an arrangement like this (AP's being initialized by a kernel
103 * thread), for a thread has its dedicated stack. (The stack used during the
104 * BSP initialization (prior the very first call to scheduler()) will be used
105 * as an initialization stack for each AP.)
106 */
[7f043c0]107void kmp(void *arg __attribute__((unused)))
[a26ddd1]108{
[c27c988]109 unsigned int i;
[6401f79]110
[a26ddd1]111 ASSERT(ops != NULL);
[fe32163]112
[a26ddd1]113 /*
114 * We need to access data in frame 0.
115 * We boldly make use of kernel address space mapping.
116 */
[fe32163]117
[a26ddd1]118 /*
119 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
120 */
[4bb31f7]121 *((uint16_t *) (PA2KA(0x467 + 0))) =
[fe32163]122 (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */
123 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */
[a26ddd1]124
125 /*
126 * Save 0xa to address 0xf of the CMOS RAM.
127 * BIOS will not do the POST after the INIT signal.
128 */
[fe32163]129 pio_write_8((ioport8_t *) 0x70, 0xf);
130 pio_write_8((ioport8_t *) 0x71, 0xa);
131
[a26ddd1]132 pic_disable_irqs(0xffff);
133 apic_init();
[7f043c0]134
135 uint8_t apic = l_apic_id();
[fe32163]136
137 for (i = 0; i < config.cpu_count; i++) {
[a26ddd1]138 /*
139 * Skip processors marked unusable.
140 */
141 if (!ops->cpu_enabled(i))
142 continue;
[fe32163]143
[a26ddd1]144 /*
145 * The bootstrap processor is already up.
146 */
147 if (ops->cpu_bootstrap(i))
148 continue;
[fe32163]149
[7f043c0]150 if (ops->cpu_apic_id(i) == apic) {
[4bb31f7]151 printf("%s: bad processor entry #%u, will not send IPI "
152 "to myself\n", __FUNCTION__, i);
[a26ddd1]153 continue;
154 }
155
156 /*
157 * Prepare new GDT for CPU in question.
158 */
[5f0f29ce]159
160 /* XXX Flag FRAME_LOW_4_GiB was removed temporarily,
161 * it needs to be replaced by a generic fuctionality of
162 * the memory subsystem
163 */
[fe32163]164 descriptor_t *gdt_new =
165 (descriptor_t *) malloc(GDT_ITEMS * sizeof(descriptor_t),
166 FRAME_ATOMIC);
[4bb31f7]167 if (!gdt_new)
[f651e80]168 panic("Cannot allocate memory for GDT.");
[fe32163]169
[99d6fd0]170 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(descriptor_t));
171 memsetb(&gdt_new[TSS_DES], sizeof(descriptor_t), 0);
172 protected_ap_gdtr.limit = GDT_ITEMS * sizeof(descriptor_t);
[7f1c620]173 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
174 gdtr.base = (uintptr_t) gdt_new;
[fe32163]175
[a26ddd1]176 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
177 /*
[c0b45fa]178 * There may be just one AP being initialized at
[a26ddd1]179 * the time. After it comes completely up, it is
180 * supposed to wake us up.
[c0b45fa]181 */
[4bb31f7]182 if (waitq_sleep_timeout(&ap_completion_wq, 1000000,
183 SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
184 printf("%s: waiting for cpu%u (APIC ID = %d) "
[fe32163]185 "timed out\n", __FUNCTION__, i,
[4bb31f7]186 ops->cpu_apic_id(i));
[7f043c0]187 }
[c0b45fa]188 } else
[4bb31f7]189 printf("INIT IPI for l_apic%d failed\n",
190 ops->cpu_apic_id(i));
[a26ddd1]191 }
192}
[ed0dd65]193
[623b49f1]194int smp_irq_to_pin(unsigned int irq)
[a83a802]195{
196 ASSERT(ops != NULL);
197 return ops->irq_to_pin(irq);
198}
199
[5f85c91]200#endif /* CONFIG_SMP */
[b45c443]201
[06e1e95]202/** @}
[b45c443]203 */
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