source: mainline/kernel/arch/ia32/src/smp/smp.c@ 3ee8a075

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3ee8a075 was 7f043c0, checked in by Martin Decky <martin@…>, 18 years ago

fix ICC compilation

  • Property mode set to 100644
File size: 5.4 KB
RevLine 
[ed0dd65]1/*
[df4ed85]2 * Copyright (c) 2005 Jakub Jermar
[ed0dd65]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[ed0dd65]35#include <smp/smp.h>
[a26ddd1]36#include <arch/smp/smp.h>
37#include <arch/smp/mps.h>
38#include <arch/smp/ap.h>
[66def8d]39#include <arch/boot/boot.h>
[e16e036a]40#include <genarch/acpi/acpi.h>
41#include <genarch/acpi/madt.h>
[ed0dd65]42#include <config.h>
[a26ddd1]43#include <synch/waitq.h>
[6153749]44#include <synch/synch.h>
[a26ddd1]45#include <arch/pm.h>
46#include <func.h>
47#include <panic.h>
48#include <debug.h>
49#include <arch/asm.h>
50#include <mm/frame.h>
51#include <mm/page.h>
[085d973]52#include <mm/slab.h>
[fc1e4f6]53#include <mm/as.h>
[9c0a9b3]54#include <print.h>
55#include <memstr.h>
[80d31883]56#include <arch/drivers/i8259.h>
[ed0dd65]57
[5f85c91]58#ifdef CONFIG_SMP
[ed0dd65]59
[a26ddd1]60static struct smp_config_operations *ops = NULL;
61
[ed0dd65]62void smp_init(void)
63{
[7f1c620]64 uintptr_t l_apic_address, io_apic_address;
[6a22fcb]65
[ed0dd65]66 if (acpi_madt) {
67 acpi_madt_parse();
[232e3ec7]68 ops = &madt_config_operations;
[ed0dd65]69 }
[a26ddd1]70 if (config.cpu_count == 1) {
[ed0dd65]71 mps_init();
[a26ddd1]72 ops = &mps_config_operations;
73 }
[7d365305]74
[7f1c620]75 l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
[e45f81a]76 if (!l_apic_address)
[6a22fcb]77 panic("cannot allocate address for l_apic\n");
78
[7f1c620]79 io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA);
[e45f81a]80 if (!io_apic_address)
[6a22fcb]81 panic("cannot allocate address for io_apic\n");
82
[946b630]83 if (config.cpu_count > 1) {
[7f1c620]84 page_mapping_insert(AS_KERNEL, l_apic_address, (uintptr_t) l_apic,
[7cb567cd]85 PAGE_NOT_CACHEABLE | PAGE_WRITE);
[7f1c620]86 page_mapping_insert(AS_KERNEL, io_apic_address, (uintptr_t) io_apic,
[7cb567cd]87 PAGE_NOT_CACHEABLE | PAGE_WRITE);
[6a22fcb]88
[7f1c620]89 l_apic = (uint32_t *) l_apic_address;
90 io_apic = (uint32_t *) io_apic_address;
[7cb567cd]91 }
[ed0dd65]92}
93
[a26ddd1]94/*
95 * Kernel thread for bringing up application processors. It becomes clear
96 * that we need an arrangement like this (AP's being initialized by a kernel
97 * thread), for a thread has its dedicated stack. (The stack used during the
98 * BSP initialization (prior the very first call to scheduler()) will be used
99 * as an initialization stack for each AP.)
100 */
[7f043c0]101void kmp(void *arg __attribute__((unused)))
[a26ddd1]102{
[c27c988]103 unsigned int i;
[6401f79]104
[a26ddd1]105 ASSERT(ops != NULL);
106
107 /*
108 * We need to access data in frame 0.
109 * We boldly make use of kernel address space mapping.
110 */
111
112 /*
113 * Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
114 */
[7f043c0]115 *((uint16_t *) (PA2KA(0x467 + 0))) = (uint16_t) (((uintptr_t) ap_boot) >> 4); /* segment */
116 *((uint16_t *) (PA2KA(0x467 + 2))) = 0; /* offset */
[a26ddd1]117
118 /*
119 * Save 0xa to address 0xf of the CMOS RAM.
120 * BIOS will not do the POST after the INIT signal.
121 */
[f619ec11]122 outb(0x70, 0xf);
123 outb(0x71, 0xa);
[a26ddd1]124
125 pic_disable_irqs(0xffff);
126 apic_init();
[7f043c0]127
128 uint8_t apic = l_apic_id();
[a26ddd1]129
130 for (i = 0; i < ops->cpu_count(); i++) {
131 struct descriptor *gdt_new;
132
133 /*
134 * Skip processors marked unusable.
135 */
136 if (!ops->cpu_enabled(i))
137 continue;
138
139 /*
140 * The bootstrap processor is already up.
141 */
142 if (ops->cpu_bootstrap(i))
143 continue;
144
[7f043c0]145 if (ops->cpu_apic_id(i) == apic) {
146 printf("%s: bad processor entry #%u, will not send IPI to myself\n", __FUNCTION__, i);
[a26ddd1]147 continue;
148 }
149
150 /*
151 * Prepare new GDT for CPU in question.
152 */
[7f043c0]153 if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS * sizeof(struct descriptor), FRAME_ATOMIC)))
[a26ddd1]154 panic("couldn't allocate memory for GDT\n");
155
[66def8d]156 memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor));
[7f1c620]157 memsetb((uintptr_t)(&gdt_new[TSS_DES]), sizeof(struct descriptor), 0);
[66def8d]158 protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor);
[7f1c620]159 protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new);
160 gdtr.base = (uintptr_t) gdt_new;
[a26ddd1]161
162 if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
163 /*
[c0b45fa]164 * There may be just one AP being initialized at
[a26ddd1]165 * the time. After it comes completely up, it is
166 * supposed to wake us up.
[c0b45fa]167 */
[7f043c0]168 if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) {
169 unsigned int cpu = (config.cpu_active > i) ? config.cpu_active : i;
170 printf("%s: waiting for cpu%u (APIC ID = %d) timed out\n", __FUNCTION__, cpu, ops->cpu_apic_id(i));
171 }
[c0b45fa]172 } else
[a26ddd1]173 printf("INIT IPI for l_apic%d failed\n", ops->cpu_apic_id(i));
174 }
175}
[ed0dd65]176
[623b49f1]177int smp_irq_to_pin(unsigned int irq)
[a83a802]178{
179 ASSERT(ops != NULL);
180 return ops->irq_to_pin(irq);
181}
182
[5f85c91]183#endif /* CONFIG_SMP */
[b45c443]184
[06e1e95]185/** @}
[b45c443]186 */
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