[f761f1eb] | 1 | /*
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[4bb31f7] | 2 | * Copyright (c) 2008 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[06e1e95] | 29 | /** @addtogroup ia32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[5f85c91] | 35 | #ifdef CONFIG_SMP
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[f761f1eb] | 36 |
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| 37 | #include <config.h>
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| 38 | #include <print.h>
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[a26ddd1] | 39 | #include <debug.h>
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[ed0dd65] | 40 | #include <arch/smp/mps.h>
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[397c77f] | 41 | #include <arch/smp/apic.h>
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[a26ddd1] | 42 | #include <arch/smp/smp.h>
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[f761f1eb] | 43 | #include <func.h>
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| 44 | #include <arch/types.h>
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| 45 | #include <cpu.h>
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| 46 | #include <arch/asm.h>
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[dba84ff] | 47 | #include <arch/bios/bios.h>
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[9c0a9b3] | 48 | #include <mm/frame.h>
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[f761f1eb] | 49 |
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| 50 | /*
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[ed0dd65] | 51 | * MultiProcessor Specification detection code.
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[f761f1eb] | 52 | */
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| 53 |
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| 54 | #define FS_SIGNATURE 0x5f504d5f
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| 55 | #define CT_SIGNATURE 0x504d4350
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| 56 |
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[7f043c0] | 57 | static int mps_fs_check(uint8_t *base);
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| 58 | static int mps_ct_check(void);
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[f761f1eb] | 59 |
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[7f043c0] | 60 | static int configure_via_ct(void);
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| 61 | static int configure_via_default(uint8_t n);
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[f761f1eb] | 62 |
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[7f043c0] | 63 | static int ct_processor_entry(struct __processor_entry *pr);
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| 64 | static void ct_bus_entry(struct __bus_entry *bus);
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| 65 | static void ct_io_apic_entry(struct __io_apic_entry *ioa);
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| 66 | static void ct_io_intr_entry(struct __io_intr_entry *iointr);
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| 67 | static void ct_l_intr_entry(struct __l_intr_entry *lintr);
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[f761f1eb] | 68 |
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[7f043c0] | 69 | static void ct_extended_entries(void);
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[f761f1eb] | 70 |
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[ed0dd65] | 71 | static struct mps_fs *fs;
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| 72 | static struct mps_ct *ct;
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[f761f1eb] | 73 |
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| 74 | struct __processor_entry *processor_entries = NULL;
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| 75 | struct __bus_entry *bus_entries = NULL;
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| 76 | struct __io_apic_entry *io_apic_entries = NULL;
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| 77 | struct __io_intr_entry *io_intr_entries = NULL;
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| 78 | struct __l_intr_entry *l_intr_entries = NULL;
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| 79 |
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[3802fcd] | 80 | unsigned int processor_entry_cnt = 0;
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| 81 | unsigned int bus_entry_cnt = 0;
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| 82 | unsigned int io_apic_entry_cnt = 0;
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| 83 | unsigned int io_intr_entry_cnt = 0;
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| 84 | unsigned int l_intr_entry_cnt = 0;
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[f761f1eb] | 85 |
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[a26ddd1] | 86 | /*
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| 87 | * Implementation of IA-32 SMP configuration interface.
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| 88 | */
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[98000fb] | 89 | static size_t get_cpu_count(void);
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| 90 | static bool is_cpu_enabled(size_t i);
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| 91 | static bool is_bsp(size_t i);
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| 92 | static uint8_t get_cpu_apic_id(size_t i);
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[623b49f1] | 93 | static int mps_irq_to_pin(unsigned int irq);
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[a26ddd1] | 94 |
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| 95 | struct smp_config_operations mps_config_operations = {
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| 96 | .cpu_count = get_cpu_count,
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| 97 | .cpu_enabled = is_cpu_enabled,
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| 98 | .cpu_bootstrap = is_bsp,
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[a83a802] | 99 | .cpu_apic_id = get_cpu_apic_id,
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| 100 | .irq_to_pin = mps_irq_to_pin
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[a26ddd1] | 101 | };
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| 102 |
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[98000fb] | 103 | size_t get_cpu_count(void)
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[a26ddd1] | 104 | {
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| 105 | return processor_entry_cnt;
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| 106 | }
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| 107 |
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[98000fb] | 108 | bool is_cpu_enabled(size_t i)
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[a26ddd1] | 109 | {
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| 110 | ASSERT(i < processor_entry_cnt);
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[7f043c0] | 111 | return (bool) ((processor_entries[i].cpu_flags & 0x01) == 0x01);
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[a26ddd1] | 112 | }
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| 113 |
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[98000fb] | 114 | bool is_bsp(size_t i)
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[a26ddd1] | 115 | {
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| 116 | ASSERT(i < processor_entry_cnt);
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[7f043c0] | 117 | return (bool) ((processor_entries[i].cpu_flags & 0x02) == 0x02);
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[a26ddd1] | 118 | }
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| 119 |
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[98000fb] | 120 | uint8_t get_cpu_apic_id(size_t i)
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[a26ddd1] | 121 | {
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| 122 | ASSERT(i < processor_entry_cnt);
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| 123 | return processor_entries[i].l_apic_id;
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| 124 | }
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| 125 |
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| 126 |
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[f761f1eb] | 127 | /*
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| 128 | * Used to check the integrity of the MP Floating Structure.
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| 129 | */
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[7f1c620] | 130 | int mps_fs_check(uint8_t *base)
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[f761f1eb] | 131 | {
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[3802fcd] | 132 | unsigned int i;
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[7f1c620] | 133 | uint8_t sum;
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[f761f1eb] | 134 |
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| 135 | for (i = 0, sum = 0; i < 16; i++)
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[7f043c0] | 136 | sum = (uint8_t) (sum + base[i]);
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[f761f1eb] | 137 |
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| 138 | return !sum;
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| 139 | }
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| 140 |
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| 141 | /*
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| 142 | * Used to check the integrity of the MP Configuration Table.
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| 143 | */
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[ed0dd65] | 144 | int mps_ct_check(void)
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[f761f1eb] | 145 | {
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[7f1c620] | 146 | uint8_t *base = (uint8_t *) ct;
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| 147 | uint8_t *ext = base + ct->base_table_length;
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| 148 | uint8_t sum;
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[f761f1eb] | 149 | int i;
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| 150 |
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| 151 | /* count the checksum for the base table */
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[4bb31f7] | 152 | for (i = 0,sum = 0; i < ct->base_table_length; i++)
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[7f043c0] | 153 | sum = (uint8_t) (sum + base[i]);
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[f761f1eb] | 154 |
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| 155 | if (sum)
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| 156 | return 0;
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| 157 |
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| 158 | /* count the checksum for the extended table */
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[4bb31f7] | 159 | for (i = 0, sum = 0; i < ct->ext_table_length; i++)
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[7f043c0] | 160 | sum = (uint8_t) (sum + ext[i]);
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[f761f1eb] | 161 |
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[f5075fa] | 162 | return sum == ct->ext_table_checksum;
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[f761f1eb] | 163 | }
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| 164 |
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[ed0dd65] | 165 | void mps_init(void)
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[f761f1eb] | 166 | {
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[7f1c620] | 167 | uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) };
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[3802fcd] | 168 | unsigned int i, j, length[2] = { 1024, 64 * 1024 };
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[f761f1eb] | 169 |
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| 170 |
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| 171 | /*
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[babcb148] | 172 | * Find MP Floating Pointer Structure
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| 173 | * 1a. search first 1K of EBDA
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| 174 | * 1b. if EBDA is undefined, search last 1K of base memory
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| 175 | * 2. search 64K starting at 0xf0000
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[f761f1eb] | 176 | */
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[babcb148] | 177 |
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[7f1c620] | 178 | addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024);
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[babcb148] | 179 | for (i = 0; i < 2; i++) {
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| 180 | for (j = 0; j < length[i]; j += 16) {
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[4bb31f7] | 181 | if (*((uint32_t *) &addr[i][j]) ==
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| 182 | FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
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[ed0dd65] | 183 | fs = (struct mps_fs *) &addr[i][j];
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[dba84ff] | 184 | goto fs_found;
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[babcb148] | 185 | }
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[dba84ff] | 186 | }
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[f761f1eb] | 187 | }
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| 188 |
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| 189 | return;
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| 190 |
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| 191 | fs_found:
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[cf85e24c] | 192 | printf("%p: MPS Floating Pointer Structure\n", fs);
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[f761f1eb] | 193 |
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| 194 | if (fs->config_type == 0 && fs->configuration_table) {
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| 195 | if (fs->mpfib2 >> 7) {
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[3ee8a075] | 196 | printf("%s: PIC mode not supported\n", __func__);
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[f761f1eb] | 197 | return;
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| 198 | }
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| 199 |
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[7f1c620] | 200 | ct = (struct mps_ct *)PA2KA((uintptr_t)fs->configuration_table);
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[f761f1eb] | 201 | config.cpu_count = configure_via_ct();
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| 202 | }
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| 203 | else
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| 204 | config.cpu_count = configure_via_default(fs->config_type);
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| 205 |
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| 206 | return;
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| 207 | }
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| 208 |
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| 209 | int configure_via_ct(void)
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| 210 | {
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[7f1c620] | 211 | uint8_t *cur;
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[3802fcd] | 212 | unsigned int i, cnt;
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[f761f1eb] | 213 |
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| 214 | if (ct->signature != CT_SIGNATURE) {
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[3ee8a075] | 215 | printf("%s: bad ct->signature\n", __func__);
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[f761f1eb] | 216 | return 1;
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| 217 | }
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[ed0dd65] | 218 | if (!mps_ct_check()) {
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[3ee8a075] | 219 | printf("%s: bad ct checksum\n", __func__);
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[f761f1eb] | 220 | return 1;
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| 221 | }
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| 222 | if (ct->oem_table) {
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[3ee8a075] | 223 | printf("%s: ct->oem_table not supported\n", __func__);
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[f761f1eb] | 224 | return 1;
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| 225 | }
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| 226 |
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[7f1c620] | 227 | l_apic = (uint32_t *)(uintptr_t)ct->l_apic;
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[f761f1eb] | 228 |
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| 229 | cnt = 0;
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| 230 | cur = &ct->base_table[0];
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[4bb31f7] | 231 | for (i = 0; i < ct->entry_count; i++) {
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[f761f1eb] | 232 | switch (*cur) {
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[4bb31f7] | 233 | /* Processor entry */
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| 234 | case 0:
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| 235 | processor_entries = processor_entries ?
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| 236 | processor_entries :
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| 237 | (struct __processor_entry *) cur;
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| 238 | processor_entry_cnt++;
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| 239 | cnt += ct_processor_entry((struct __processor_entry *)
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| 240 | cur);
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| 241 | cur += 20;
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| 242 | break;
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| 243 |
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| 244 | /* Bus entry */
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| 245 | case 1:
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| 246 | bus_entries = bus_entries ?
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| 247 | bus_entries : (struct __bus_entry *) cur;
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| 248 | bus_entry_cnt++;
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| 249 | ct_bus_entry((struct __bus_entry *) cur);
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| 250 | cur += 8;
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| 251 | break;
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[f761f1eb] | 252 |
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[4bb31f7] | 253 | /* I/O Apic */
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| 254 | case 2:
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| 255 | io_apic_entries = io_apic_entries ?
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| 256 | io_apic_entries : (struct __io_apic_entry *) cur;
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[f761f1eb] | 257 | io_apic_entry_cnt++;
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[4bb31f7] | 258 | ct_io_apic_entry((struct __io_apic_entry *) cur);
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| 259 | cur += 8;
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| 260 | break;
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[f761f1eb] | 261 |
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[4bb31f7] | 262 | /* I/O Interrupt Assignment */
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| 263 | case 3:
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| 264 | io_intr_entries = io_intr_entries ?
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| 265 | io_intr_entries : (struct __io_intr_entry *) cur;
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| 266 | io_intr_entry_cnt++;
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| 267 | ct_io_intr_entry((struct __io_intr_entry *) cur);
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| 268 | cur += 8;
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| 269 | break;
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| 270 |
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| 271 | /* Local Interrupt Assignment */
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| 272 | case 4:
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| 273 | l_intr_entries = l_intr_entries ?
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| 274 | l_intr_entries : (struct __l_intr_entry *) cur;
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| 275 | l_intr_entry_cnt++;
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| 276 | ct_l_intr_entry((struct __l_intr_entry *) cur);
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| 277 | cur += 8;
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| 278 | break;
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| 279 |
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| 280 | default:
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| 281 | /*
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| 282 | * Something is wrong. Fallback to UP mode.
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| 283 | */
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| 284 |
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| 285 | printf("%s: ct badness\n", __func__);
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| 286 | return 1;
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[f761f1eb] | 287 | }
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| 288 | }
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| 289 |
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| 290 | /*
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| 291 | * Process extended entries.
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| 292 | */
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| 293 | ct_extended_entries();
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| 294 | return cnt;
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| 295 | }
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| 296 |
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[7f043c0] | 297 | int configure_via_default(uint8_t n __attribute__((unused)))
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[f761f1eb] | 298 | {
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| 299 | /*
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| 300 | * Not yet implemented.
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| 301 | */
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[3ee8a075] | 302 | printf("%s: not supported\n", __func__);
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[f761f1eb] | 303 | return 1;
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| 304 | }
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| 305 |
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| 306 |
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[7f043c0] | 307 | int ct_processor_entry(struct __processor_entry *pr __attribute__((unused)))
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[f761f1eb] | 308 | {
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| 309 | /*
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| 310 | * Ignore processors which are not marked enabled.
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| 311 | */
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[4bb31f7] | 312 | if ((pr->cpu_flags & (1 << 0)) == 0)
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[f761f1eb] | 313 | return 0;
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| 314 |
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[4bb31f7] | 315 | apic_id_mask |= (1 << pr->l_apic_id);
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[f761f1eb] | 316 | return 1;
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| 317 | }
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| 318 |
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[7f043c0] | 319 | void ct_bus_entry(struct __bus_entry *bus __attribute__((unused)))
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[f761f1eb] | 320 | {
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[ed0dd65] | 321 | #ifdef MPSCT_VERBOSE
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[f761f1eb] | 322 | char buf[7];
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[9756131] | 323 | memcpy((void *) buf, (void *) bus->bus_type, 6);
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[f761f1eb] | 324 | buf[6] = 0;
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| 325 | printf("bus%d: %s\n", bus->bus_id, buf);
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| 326 | #endif
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| 327 | }
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| 328 |
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| 329 | void ct_io_apic_entry(struct __io_apic_entry *ioa)
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| 330 | {
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[3802fcd] | 331 | static unsigned int io_apic_count = 0;
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[f761f1eb] | 332 |
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| 333 | /* this ioapic is marked unusable */
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[5a95b25] | 334 | if ((ioa->io_apic_flags & 1) == 0)
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[f761f1eb] | 335 | return;
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| 336 |
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| 337 | if (io_apic_count++ > 0) {
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| 338 | /*
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| 339 | * Multiple IO APIC's are currently not supported.
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| 340 | */
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| 341 | return;
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| 342 | }
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| 343 |
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[7f1c620] | 344 | io_apic = (uint32_t *)(uintptr_t)ioa->io_apic;
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[f761f1eb] | 345 | }
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| 346 |
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[ed0dd65] | 347 | //#define MPSCT_VERBOSE
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[7f043c0] | 348 | void ct_io_intr_entry(struct __io_intr_entry *iointr __attribute__((unused)))
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[f761f1eb] | 349 | {
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[ed0dd65] | 350 | #ifdef MPSCT_VERBOSE
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[f761f1eb] | 351 | switch (iointr->intr_type) {
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[4bb31f7] | 352 | case 0:
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| 353 | printf("INT");
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| 354 | break;
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| 355 | case 1:
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| 356 | printf("NMI");
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| 357 | break;
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| 358 | case 2:
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| 359 | printf("SMI");
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| 360 | break;
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| 361 | case 3:
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| 362 | printf("ExtINT");
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| 363 | break;
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[f761f1eb] | 364 | }
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| 365 | putchar(',');
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[4bb31f7] | 366 | switch (iointr->poel & 3) {
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| 367 | case 0:
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| 368 | printf("bus-like");
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| 369 | break;
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| 370 | case 1:
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| 371 | printf("active high");
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| 372 | break;
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| 373 | case 2:
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| 374 | printf("reserved");
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| 375 | break;
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| 376 | case 3:
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| 377 | printf("active low");
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| 378 | break;
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[f761f1eb] | 379 | }
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| 380 | putchar(',');
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[4bb31f7] | 381 | switch ((iointr->poel >> 2) & 3) {
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| 382 | case 0:
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| 383 | printf("bus-like");
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| 384 | break;
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| 385 | case 1:
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| 386 | printf("edge-triggered");
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| 387 | break;
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| 388 | case 2:
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| 389 | printf("reserved");
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| 390 | break;
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| 391 | case 3:
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| 392 | printf("level-triggered");
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| 393 | break;
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[f761f1eb] | 394 | }
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| 395 | putchar(',');
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| 396 | printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq);
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| 397 | putchar(',');
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[4bb31f7] | 398 | printf("io_apic%d,pin%d", iointr->dst_io_apic_id,
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| 399 | iointr->dst_io_apic_pin);
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[f761f1eb] | 400 | putchar('\n');
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| 401 | #endif
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| 402 | }
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| 403 |
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[7f043c0] | 404 | void ct_l_intr_entry(struct __l_intr_entry *lintr __attribute__((unused)))
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[f761f1eb] | 405 | {
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[ed0dd65] | 406 | #ifdef MPSCT_VERBOSE
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[f761f1eb] | 407 | switch (lintr->intr_type) {
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[4bb31f7] | 408 | case 0:
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| 409 | printf("INT");
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| 410 | break;
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| 411 | case 1:
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| 412 | printf("NMI");
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| 413 | break;
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| 414 | case 2:
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| 415 | printf("SMI");
|
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| 416 | break;
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| 417 | case 3:
|
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| 418 | printf("ExtINT");
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| 419 | break;
|
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[f761f1eb] | 420 | }
|
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| 421 | putchar(',');
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[4bb31f7] | 422 | switch (lintr->poel & 3) {
|
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| 423 | case 0:
|
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| 424 | printf("bus-like");
|
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| 425 | break;
|
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| 426 | case 1:
|
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| 427 | printf("active high");
|
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| 428 | break;
|
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| 429 | case 2:
|
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| 430 | printf("reserved");
|
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| 431 | break;
|
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| 432 | case 3:
|
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| 433 | printf("active low");
|
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| 434 | break;
|
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[f761f1eb] | 435 | }
|
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| 436 | putchar(',');
|
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[4bb31f7] | 437 | switch ((lintr->poel >> 2) & 3) {
|
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| 438 | case 0:
|
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| 439 | printf("bus-like");
|
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| 440 | break;
|
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| 441 | case 1:
|
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| 442 | printf("edge-triggered");
|
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| 443 | break;
|
---|
| 444 | case 2:
|
---|
| 445 | printf("reserved");
|
---|
| 446 | break;
|
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| 447 | case 3:
|
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| 448 | printf("level-triggered");
|
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| 449 | break;
|
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[f761f1eb] | 450 | }
|
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| 451 | putchar(',');
|
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| 452 | printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq);
|
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| 453 | putchar(',');
|
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| 454 | printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
|
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| 455 | putchar('\n');
|
---|
| 456 | #endif
|
---|
| 457 | }
|
---|
| 458 |
|
---|
| 459 | void ct_extended_entries(void)
|
---|
| 460 | {
|
---|
[7f1c620] | 461 | uint8_t *ext = (uint8_t *) ct + ct->base_table_length;
|
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| 462 | uint8_t *cur;
|
---|
[8a78e68] | 463 |
|
---|
[4bb31f7] | 464 | for (cur = ext; cur < ext + ct->ext_table_length;
|
---|
| 465 | cur += cur[CT_EXT_ENTRY_LEN]) {
|
---|
[8a78e68] | 466 | switch (cur[CT_EXT_ENTRY_TYPE]) {
|
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[4bb31f7] | 467 | default:
|
---|
| 468 | printf("%p: skipping MP Configuration Table extended "
|
---|
| 469 | "entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
|
---|
| 470 | break;
|
---|
[8a78e68] | 471 | }
|
---|
| 472 | }
|
---|
[f761f1eb] | 473 | }
|
---|
| 474 |
|
---|
[623b49f1] | 475 | int mps_irq_to_pin(unsigned int irq)
|
---|
[f761f1eb] | 476 | {
|
---|
[3802fcd] | 477 | unsigned int i;
|
---|
[f761f1eb] | 478 |
|
---|
[623b49f1] | 479 | for (i = 0; i < io_intr_entry_cnt; i++) {
|
---|
[4bb31f7] | 480 | if (io_intr_entries[i].src_bus_irq == irq &&
|
---|
| 481 | io_intr_entries[i].intr_type == 0)
|
---|
[f761f1eb] | 482 | return io_intr_entries[i].dst_io_apic_pin;
|
---|
| 483 | }
|
---|
| 484 |
|
---|
| 485 | return -1;
|
---|
| 486 | }
|
---|
| 487 |
|
---|
[5f85c91] | 488 | #endif /* CONFIG_SMP */
|
---|
[b45c443] | 489 |
|
---|
[06e1e95] | 490 | /** @}
|
---|
[b45c443] | 491 | */
|
---|