[f761f1eb] | 1 | /*
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[4bb31f7] | 2 | * Copyright (c) 2008 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_ia32
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[5f85c91] | 35 | #ifdef CONFIG_SMP
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[f761f1eb] | 36 |
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| 37 | #include <config.h>
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[b2fa1204] | 38 | #include <log.h>
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[ed0dd65] | 39 | #include <arch/smp/mps.h>
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[397c77f] | 40 | #include <arch/smp/apic.h>
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[a26ddd1] | 41 | #include <arch/smp/smp.h>
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[63e27ef] | 42 | #include <assert.h>
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[b2e121a] | 43 | #include <halt.h>
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[d99c1d2] | 44 | #include <typedefs.h>
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[f761f1eb] | 45 | #include <cpu.h>
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| 46 | #include <arch/asm.h>
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[dba84ff] | 47 | #include <arch/bios/bios.h>
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[9c0a9b3] | 48 | #include <mm/frame.h>
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[f761f1eb] | 49 |
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| 50 | /*
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[ed0dd65] | 51 | * MultiProcessor Specification detection code.
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[f761f1eb] | 52 | */
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| 53 |
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[dc0b964] | 54 | #define FS_SIGNATURE UINT32_C(0x5f504d5f)
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| 55 | #define CT_SIGNATURE UINT32_C(0x504d4350)
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[f761f1eb] | 56 |
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[ed0dd65] | 57 | static struct mps_fs *fs;
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| 58 | static struct mps_ct *ct;
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[f761f1eb] | 59 |
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[fe32163] | 60 | static struct __processor_entry *processor_entries = NULL;
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| 61 | static struct __bus_entry *bus_entries = NULL;
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| 62 | static struct __io_apic_entry *io_apic_entries = NULL;
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| 63 | static struct __io_intr_entry *io_intr_entries = NULL;
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| 64 | static struct __l_intr_entry *l_intr_entries = NULL;
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[f761f1eb] | 65 |
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[fe32163] | 66 | static size_t io_apic_cnt = 0;
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[f761f1eb] | 67 |
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[fe32163] | 68 | static size_t processor_entry_cnt = 0;
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| 69 | static size_t bus_entry_cnt = 0;
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| 70 | static size_t io_apic_entry_cnt = 0;
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| 71 | static size_t io_intr_entry_cnt = 0;
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| 72 | static size_t l_intr_entry_cnt = 0;
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[a26ddd1] | 73 |
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[0a79ad9] | 74 | static uint8_t mps_cpu_apic_id(size_t i)
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[a26ddd1] | 75 | {
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[63e27ef] | 76 | assert(i < processor_entry_cnt);
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[a35b458] | 77 |
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[fe32163] | 78 | return processor_entries[i].l_apic_id;
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[a26ddd1] | 79 | }
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| 80 |
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[0a79ad9] | 81 | static bool mps_cpu_enabled(size_t i)
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[a26ddd1] | 82 | {
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[63e27ef] | 83 | assert(i < processor_entry_cnt);
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[a35b458] | 84 |
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[fe32163] | 85 | /*
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| 86 | * FIXME: The current local APIC driver limits usable
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[4edd57fd] | 87 | * CPU IDs to 8.
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[fe32163] | 88 | *
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| 89 | */
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[4edd57fd] | 90 | if (i > 7)
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[fe32163] | 91 | return false;
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[a35b458] | 92 |
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[c81132d] | 93 | return ((processor_entries[i].cpu_flags & 0x01) == 0x01);
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[a26ddd1] | 94 | }
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| 95 |
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[0a79ad9] | 96 | static bool mps_cpu_bootstrap(size_t i)
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[a26ddd1] | 97 | {
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[63e27ef] | 98 | assert(i < processor_entry_cnt);
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[a35b458] | 99 |
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[c81132d] | 100 | return ((processor_entries[i].cpu_flags & 0x02) == 0x02);
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[a26ddd1] | 101 | }
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| 102 |
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[fe32163] | 103 | static int mps_irq_to_pin(unsigned int irq)
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[a26ddd1] | 104 | {
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[fe32163] | 105 | size_t i;
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[a35b458] | 106 |
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[fe32163] | 107 | for (i = 0; i < io_intr_entry_cnt; i++) {
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| 108 | if (io_intr_entries[i].src_bus_irq == irq &&
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| 109 | io_intr_entries[i].intr_type == 0)
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| 110 | return io_intr_entries[i].dst_io_apic_pin;
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| 111 | }
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[a35b458] | 112 |
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[fe32163] | 113 | return -1;
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[a26ddd1] | 114 | }
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| 115 |
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[fe32163] | 116 | /** Implementation of IA-32 SMP configuration interface.
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| 117 | *
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| 118 | */
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| 119 | struct smp_config_operations mps_config_operations = {
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[0a79ad9] | 120 | .cpu_enabled = mps_cpu_enabled,
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| 121 | .cpu_bootstrap = mps_cpu_bootstrap,
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| 122 | .cpu_apic_id = mps_cpu_apic_id,
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[fe32163] | 123 | .irq_to_pin = mps_irq_to_pin
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| 124 | };
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[a26ddd1] | 125 |
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[fe32163] | 126 | /** Check the integrity of the MP Floating Structure.
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| 127 | *
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[f761f1eb] | 128 | */
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[fe32163] | 129 | static bool mps_fs_check(uint8_t *base)
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[f761f1eb] | 130 | {
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[3802fcd] | 131 | unsigned int i;
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[7f1c620] | 132 | uint8_t sum;
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[a35b458] | 133 |
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[f761f1eb] | 134 | for (i = 0, sum = 0; i < 16; i++)
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[7f043c0] | 135 | sum = (uint8_t) (sum + base[i]);
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[a35b458] | 136 |
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[fe32163] | 137 | return (sum == 0);
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[f761f1eb] | 138 | }
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| 139 |
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[fe32163] | 140 | /** Check the integrity of the MP Configuration Table.
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| 141 | *
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[f761f1eb] | 142 | */
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[fe32163] | 143 | static bool mps_ct_check(void)
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[f761f1eb] | 144 | {
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[7f1c620] | 145 | uint8_t *base = (uint8_t *) ct;
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| 146 | uint8_t *ext = base + ct->base_table_length;
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| 147 | uint8_t sum;
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[fe32163] | 148 | uint16_t i;
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[a35b458] | 149 |
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[fe32163] | 150 | /* Compute the checksum for the base table */
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| 151 | for (i = 0, sum = 0; i < ct->base_table_length; i++)
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[7f043c0] | 152 | sum = (uint8_t) (sum + base[i]);
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[a35b458] | 153 |
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[f761f1eb] | 154 | if (sum)
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[fe32163] | 155 | return false;
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[a35b458] | 156 |
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[fe32163] | 157 | /* Compute the checksum for the extended table */
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[4bb31f7] | 158 | for (i = 0, sum = 0; i < ct->ext_table_length; i++)
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[7f043c0] | 159 | sum = (uint8_t) (sum + ext[i]);
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[a35b458] | 160 |
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[fe32163] | 161 | return (sum == ct->ext_table_checksum);
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[f761f1eb] | 162 | }
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| 163 |
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[fe32163] | 164 | static void ct_processor_entry(struct __processor_entry *pr)
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[f761f1eb] | 165 | {
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| 166 | /*
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| 167 | * Ignore processors which are not marked enabled.
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| 168 | */
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[4bb31f7] | 169 | if ((pr->cpu_flags & (1 << 0)) == 0)
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[fe32163] | 170 | return;
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[a35b458] | 171 |
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[fe32163] | 172 | apic_id_mask |= (1 << pr->l_apic_id);
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[f761f1eb] | 173 | }
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| 174 |
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[fe32163] | 175 | static void ct_bus_entry(struct __bus_entry *bus __attribute__((unused)))
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[f761f1eb] | 176 | {
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[ed0dd65] | 177 | #ifdef MPSCT_VERBOSE
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[f761f1eb] | 178 | char buf[7];
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[a35b458] | 179 |
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[9756131] | 180 | memcpy((void *) buf, (void *) bus->bus_type, 6);
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[f761f1eb] | 181 | buf[6] = 0;
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[a35b458] | 182 |
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[b2fa1204] | 183 | log(LF_ARCH, LVL_DEBUG, "MPS: bus=%" PRIu8 " (%s)", bus->bus_id, buf);
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[f761f1eb] | 184 | #endif
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| 185 | }
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| 186 |
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[fe32163] | 187 | static void ct_io_apic_entry(struct __io_apic_entry *ioa)
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[f761f1eb] | 188 | {
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[fe32163] | 189 | /* This I/O APIC is marked unusable */
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[5a95b25] | 190 | if ((ioa->io_apic_flags & 1) == 0)
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[f761f1eb] | 191 | return;
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[a35b458] | 192 |
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[fe32163] | 193 | if (io_apic_cnt++ > 0) {
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[f761f1eb] | 194 | /*
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[fe32163] | 195 | * Multiple I/O APICs are currently not supported.
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[f761f1eb] | 196 | */
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| 197 | return;
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| 198 | }
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[a35b458] | 199 |
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[fe32163] | 200 | io_apic = (uint32_t *) (uintptr_t) ioa->io_apic;
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[f761f1eb] | 201 | }
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| 202 |
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[fe32163] | 203 | static void ct_io_intr_entry(struct __io_intr_entry *iointr
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| 204 | __attribute__((unused)))
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[f761f1eb] | 205 | {
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[ed0dd65] | 206 | #ifdef MPSCT_VERBOSE
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[b2fa1204] | 207 | log_begin(LF_ARCH, LVL_DEBUG);
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| 208 | log_printf("MPS: ");
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[a35b458] | 209 |
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[f761f1eb] | 210 | switch (iointr->intr_type) {
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[4bb31f7] | 211 | case 0:
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[b2fa1204] | 212 | log_printf("INT");
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[4bb31f7] | 213 | break;
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| 214 | case 1:
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[b2fa1204] | 215 | log_printf("NMI");
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[4bb31f7] | 216 | break;
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| 217 | case 2:
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[b2fa1204] | 218 | log_printf("SMI");
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[4bb31f7] | 219 | break;
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| 220 | case 3:
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[b2fa1204] | 221 | log_printf("ExtINT");
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[4bb31f7] | 222 | break;
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[f761f1eb] | 223 | }
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[a35b458] | 224 |
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[b2fa1204] | 225 | log_printf(", ");
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[a35b458] | 226 |
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[4bb31f7] | 227 | switch (iointr->poel & 3) {
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| 228 | case 0:
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[b2fa1204] | 229 | log_printf("bus-like");
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[4bb31f7] | 230 | break;
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| 231 | case 1:
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[b2fa1204] | 232 | log_printf("active high");
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[4bb31f7] | 233 | break;
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| 234 | case 2:
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[b2fa1204] | 235 | log_printf("reserved");
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[4bb31f7] | 236 | break;
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| 237 | case 3:
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[b2fa1204] | 238 | log_printf("active low");
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[4bb31f7] | 239 | break;
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[f761f1eb] | 240 | }
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[a35b458] | 241 |
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[b2fa1204] | 242 | log_printf(", ");
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[a35b458] | 243 |
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[4bb31f7] | 244 | switch ((iointr->poel >> 2) & 3) {
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| 245 | case 0:
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[b2fa1204] | 246 | log_printf("bus-like");
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[4bb31f7] | 247 | break;
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| 248 | case 1:
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[b2fa1204] | 249 | log_printf("edge-triggered");
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[4bb31f7] | 250 | break;
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| 251 | case 2:
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[b2fa1204] | 252 | log_printf("reserved");
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[4bb31f7] | 253 | break;
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| 254 | case 3:
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[b2fa1204] | 255 | log_printf("level-triggered");
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[4bb31f7] | 256 | break;
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[f761f1eb] | 257 | }
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[a35b458] | 258 |
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[1433ecda] | 259 | log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8 " pin=%"
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[b2fa1204] | 260 | PRIu8, iointr->src_bus_id, iointr->src_bus_irq,
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[fe32163] | 261 | iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
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[b2fa1204] | 262 | log_end();
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[f761f1eb] | 263 | #endif
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| 264 | }
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| 265 |
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[fe32163] | 266 | static void ct_l_intr_entry(struct __l_intr_entry *lintr
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| 267 | __attribute__((unused)))
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[f761f1eb] | 268 | {
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[ed0dd65] | 269 | #ifdef MPSCT_VERBOSE
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[b2fa1204] | 270 | log_begin(LF_ARCH, LVL_DEBUG);
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| 271 | log_printf("MPS: ");
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[a35b458] | 272 |
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[f761f1eb] | 273 | switch (lintr->intr_type) {
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[4bb31f7] | 274 | case 0:
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[b2fa1204] | 275 | log_printf("INT");
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[fe32163] | 276 | break;
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[4bb31f7] | 277 | case 1:
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[b2fa1204] | 278 | log_printf("NMI");
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[fe32163] | 279 | break;
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[4bb31f7] | 280 | case 2:
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[b2fa1204] | 281 | log_printf("SMI");
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[fe32163] | 282 | break;
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[4bb31f7] | 283 | case 3:
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[b2fa1204] | 284 | log_printf("ExtINT");
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[fe32163] | 285 | break;
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[f761f1eb] | 286 | }
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[a35b458] | 287 |
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[b2fa1204] | 288 | log_printf(", ");
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[a35b458] | 289 |
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[4bb31f7] | 290 | switch (lintr->poel & 3) {
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| 291 | case 0:
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[b2fa1204] | 292 | log_printf("bus-like");
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[fe32163] | 293 | break;
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[4bb31f7] | 294 | case 1:
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[b2fa1204] | 295 | log_printf("active high");
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[fe32163] | 296 | break;
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[4bb31f7] | 297 | case 2:
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[b2fa1204] | 298 | log_printf("reserved");
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[fe32163] | 299 | break;
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[4bb31f7] | 300 | case 3:
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[b2fa1204] | 301 | log_printf("active low");
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[fe32163] | 302 | break;
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[f761f1eb] | 303 | }
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[a35b458] | 304 |
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[b2fa1204] | 305 | log_printf(", ");
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[a35b458] | 306 |
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[4bb31f7] | 307 | switch ((lintr->poel >> 2) & 3) {
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| 308 | case 0:
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[b2fa1204] | 309 | log_printf("bus-like");
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[fe32163] | 310 | break;
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[4bb31f7] | 311 | case 1:
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[b2fa1204] | 312 | log_printf("edge-triggered");
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[fe32163] | 313 | break;
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[4bb31f7] | 314 | case 2:
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[b2fa1204] | 315 | log_printf("reserved");
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[fe32163] | 316 | break;
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[4bb31f7] | 317 | case 3:
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[b2fa1204] | 318 | log_printf("level-triggered");
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[fe32163] | 319 | break;
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[f761f1eb] | 320 | }
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[a35b458] | 321 |
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[1433ecda] | 322 | log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8 " pin=%"
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[b2fa1204] | 323 | PRIu8, lintr->src_bus_id, lintr->src_bus_irq,
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[fe32163] | 324 | lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
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[b2fa1204] | 325 | log_end();
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[f761f1eb] | 326 | #endif
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| 327 | }
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| 328 |
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[fe32163] | 329 | static void ct_extended_entries(void)
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[f761f1eb] | 330 | {
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[7f1c620] | 331 | uint8_t *ext = (uint8_t *) ct + ct->base_table_length;
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| 332 | uint8_t *cur;
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[a35b458] | 333 |
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[4bb31f7] | 334 | for (cur = ext; cur < ext + ct->ext_table_length;
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| 335 | cur += cur[CT_EXT_ENTRY_LEN]) {
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[8a78e68] | 336 | switch (cur[CT_EXT_ENTRY_TYPE]) {
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[4bb31f7] | 337 | default:
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[b2fa1204] | 338 | log(LF_ARCH, LVL_NOTE, "MPS: Skipping MP Configuration"
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| 339 | " Table extended entry type %" PRIu8,
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| 340 | cur[CT_EXT_ENTRY_TYPE]);
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[fe32163] | 341 | }
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| 342 | }
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| 343 | }
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| 344 |
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| 345 | static void configure_via_ct(void)
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| 346 | {
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| 347 | if (ct->signature != CT_SIGNATURE) {
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[b2fa1204] | 348 | log(LF_ARCH, LVL_WARN, "MPS: Wrong ct->signature");
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[fe32163] | 349 | return;
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| 350 | }
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[a35b458] | 351 |
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[fe32163] | 352 | if (!mps_ct_check()) {
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[b2fa1204] | 353 | log(LF_ARCH, LVL_WARN, "MPS: Wrong ct checksum");
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[fe32163] | 354 | return;
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| 355 | }
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[a35b458] | 356 |
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[fe32163] | 357 | if (ct->oem_table) {
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[b2fa1204] | 358 | log(LF_ARCH, LVL_WARN, "MPS: ct->oem_table not supported");
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[fe32163] | 359 | return;
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| 360 | }
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[a35b458] | 361 |
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[fe32163] | 362 | l_apic = (uint32_t *) (uintptr_t) ct->l_apic;
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[a35b458] | 363 |
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[fe32163] | 364 | uint8_t *cur = &ct->base_table[0];
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| 365 | uint16_t i;
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[a35b458] | 366 |
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[fe32163] | 367 | for (i = 0; i < ct->entry_count; i++) {
|
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| 368 | switch (*cur) {
|
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| 369 | case 0: /* Processor entry */
|
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| 370 | processor_entries = processor_entries ?
|
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| 371 | processor_entries :
|
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| 372 | (struct __processor_entry *) cur;
|
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| 373 | processor_entry_cnt++;
|
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| 374 | ct_processor_entry((struct __processor_entry *) cur);
|
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| 375 | cur += 20;
|
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| 376 | break;
|
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| 377 | case 1: /* Bus entry */
|
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| 378 | bus_entries = bus_entries ?
|
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| 379 | bus_entries : (struct __bus_entry *) cur;
|
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| 380 | bus_entry_cnt++;
|
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| 381 | ct_bus_entry((struct __bus_entry *) cur);
|
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| 382 | cur += 8;
|
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| 383 | break;
|
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| 384 | case 2: /* I/O APIC */
|
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| 385 | io_apic_entries = io_apic_entries ?
|
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| 386 | io_apic_entries : (struct __io_apic_entry *) cur;
|
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| 387 | io_apic_entry_cnt++;
|
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| 388 | ct_io_apic_entry((struct __io_apic_entry *) cur);
|
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| 389 | cur += 8;
|
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[4bb31f7] | 390 | break;
|
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[fe32163] | 391 | case 3: /* I/O Interrupt Assignment */
|
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| 392 | io_intr_entries = io_intr_entries ?
|
---|
| 393 | io_intr_entries : (struct __io_intr_entry *) cur;
|
---|
| 394 | io_intr_entry_cnt++;
|
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| 395 | ct_io_intr_entry((struct __io_intr_entry *) cur);
|
---|
| 396 | cur += 8;
|
---|
| 397 | break;
|
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| 398 | case 4: /* Local Interrupt Assignment */
|
---|
| 399 | l_intr_entries = l_intr_entries ?
|
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| 400 | l_intr_entries : (struct __l_intr_entry *) cur;
|
---|
| 401 | l_intr_entry_cnt++;
|
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| 402 | ct_l_intr_entry((struct __l_intr_entry *) cur);
|
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| 403 | cur += 8;
|
---|
| 404 | break;
|
---|
| 405 | default:
|
---|
| 406 | /*
|
---|
| 407 | * Something is wrong. Fallback to UP mode.
|
---|
| 408 | */
|
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[b2fa1204] | 409 | log(LF_ARCH, LVL_WARN, "MPS: ct badness %" PRIu8, *cur);
|
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[fe32163] | 410 | return;
|
---|
[8a78e68] | 411 | }
|
---|
| 412 | }
|
---|
[a35b458] | 413 |
|
---|
[fe32163] | 414 | /*
|
---|
| 415 | * Process extended entries.
|
---|
| 416 | */
|
---|
| 417 | ct_extended_entries();
|
---|
[f761f1eb] | 418 | }
|
---|
| 419 |
|
---|
[fe32163] | 420 | static void configure_via_default(uint8_t n __attribute__((unused)))
|
---|
[f761f1eb] | 421 | {
|
---|
[fe32163] | 422 | /*
|
---|
| 423 | * Not yet implemented.
|
---|
| 424 | */
|
---|
[b2fa1204] | 425 | log(LF_ARCH, LVL_WARN, "MPS: Default configuration not supported");
|
---|
[fe32163] | 426 | }
|
---|
| 427 |
|
---|
| 428 | void mps_init(void)
|
---|
| 429 | {
|
---|
| 430 | uint8_t *addr[2] = { NULL, (uint8_t *) PA2KA(0xf0000) };
|
---|
[3802fcd] | 431 | unsigned int i;
|
---|
[fe32163] | 432 | unsigned int j;
|
---|
| 433 | unsigned int length[2] = { 1024, 64 * 1024 };
|
---|
[a35b458] | 434 |
|
---|
[fe32163] | 435 | /*
|
---|
| 436 | * Find MP Floating Pointer Structure
|
---|
| 437 | * 1a. search first 1K of EBDA
|
---|
| 438 | * 1b. if EBDA is undefined, search last 1K of base memory
|
---|
| 439 | * 2. search 64K starting at 0xf0000
|
---|
| 440 | */
|
---|
[a35b458] | 441 |
|
---|
[fe32163] | 442 | addr[0] = (uint8_t *) PA2KA(ebda ? ebda : 639 * 1024);
|
---|
| 443 | for (i = 0; i < 2; i++) {
|
---|
| 444 | for (j = 0; j < length[i]; j += 16) {
|
---|
| 445 | if ((*((uint32_t *) &addr[i][j]) ==
|
---|
| 446 | FS_SIGNATURE) && (mps_fs_check(&addr[i][j]))) {
|
---|
| 447 | fs = (struct mps_fs *) &addr[i][j];
|
---|
| 448 | goto fs_found;
|
---|
| 449 | }
|
---|
| 450 | }
|
---|
[f761f1eb] | 451 | }
|
---|
[a35b458] | 452 |
|
---|
[fe32163] | 453 | return;
|
---|
[a35b458] | 454 |
|
---|
[fe32163] | 455 | fs_found:
|
---|
[b2fa1204] | 456 | log(LF_ARCH, LVL_NOTE, "%p: MPS Floating Pointer Structure", fs);
|
---|
[a35b458] | 457 |
|
---|
[fe32163] | 458 | if ((fs->config_type == 0) && (fs->configuration_table)) {
|
---|
| 459 | if (fs->mpfib2 >> 7) {
|
---|
[b2fa1204] | 460 | log(LF_ARCH, LVL_WARN, "MPS: PIC mode not supported\n");
|
---|
[fe32163] | 461 | return;
|
---|
| 462 | }
|
---|
[a35b458] | 463 |
|
---|
[fe32163] | 464 | ct = (struct mps_ct *) PA2KA((uintptr_t) fs->configuration_table);
|
---|
| 465 | configure_via_ct();
|
---|
| 466 | } else
|
---|
| 467 | configure_via_default(fs->config_type);
|
---|
[a35b458] | 468 |
|
---|
[fe32163] | 469 | if (processor_entry_cnt > 0)
|
---|
| 470 | config.cpu_count = processor_entry_cnt;
|
---|
[f761f1eb] | 471 | }
|
---|
| 472 |
|
---|
[5f85c91] | 473 | #endif /* CONFIG_SMP */
|
---|
[b45c443] | 474 |
|
---|
[06e1e95] | 475 | /** @}
|
---|
[b45c443] | 476 | */
|
---|