source: mainline/kernel/arch/ia32/src/smp/apic.c@ da68871a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since da68871a was da68871a, checked in by Adam Hraska <adam.hraska+hos@…>, 13 years ago

Merged changes from mainline.
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1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <typedefs.h>
36#include <arch/smp/apic.h>
37#include <arch/smp/ap.h>
38#include <arch/smp/mps.h>
39#include <arch/boot/boot.h>
40#include <mm/page.h>
41#include <time/delay.h>
42#include <interrupt.h>
43#include <arch/interrupt.h>
44#include <print.h>
45#include <arch/asm.h>
46#include <arch.h>
47#include <ddi/irq.h>
48#include <ddi/device.h>
49
50#ifdef CONFIG_SMP
51
52/*
53 * Advanced Programmable Interrupt Controller for SMP systems.
54 * Tested on:
55 * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
56 * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
57 * VMware Workstation 5.5 with 2 CPUs
58 * QEMU 0.8.0 with 2-15 CPUs
59 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
60 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
61 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
62 *
63 */
64
65/*
66 * These variables either stay configured as initilalized, or are changed by
67 * the MP configuration code.
68 *
69 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
70 * optimize the code too much and accesses to l_apic and io_apic, that must
71 * always be 32-bit, would use byte oriented instructions.
72 *
73 */
74volatile uint32_t *l_apic = (uint32_t *) UINT32_C(0xfee00000);
75volatile uint32_t *io_apic = (uint32_t *) UINT32_C(0xfec00000);
76
77uint32_t apic_id_mask = 0;
78uint8_t bsp_l_apic = 0;
79
80static irq_t l_apic_timer_irq;
81
82static int apic_poll_errors(void);
83
84#ifdef LAPIC_VERBOSE
85static const char *delmod_str[] = {
86 "Fixed",
87 "Lowest Priority",
88 "SMI",
89 "Reserved",
90 "NMI",
91 "INIT",
92 "STARTUP",
93 "ExtInt"
94};
95
96static const char *destmod_str[] = {
97 "Physical",
98 "Logical"
99};
100
101static const char *trigmod_str[] = {
102 "Edge",
103 "Level"
104};
105
106static const char *mask_str[] = {
107 "Unmasked",
108 "Masked"
109};
110
111static const char *delivs_str[] = {
112 "Idle",
113 "Send Pending"
114};
115
116static const char *tm_mode_str[] = {
117 "One-shot",
118 "Periodic"
119};
120
121static const char *intpol_str[] = {
122 "Polarity High",
123 "Polarity Low"
124};
125#endif /* LAPIC_VERBOSE */
126
127/** APIC spurious interrupt handler.
128 *
129 * @param n Interrupt vector.
130 * @param istate Interrupted state.
131 *
132 */
133static void apic_spurious(unsigned int n __attribute__((unused)),
134 istate_t *istate __attribute__((unused)))
135{
136#ifdef CONFIG_DEBUG
137 printf("cpu%u: APIC spurious interrupt\n", CPU->id);
138#endif
139}
140
141static irq_ownership_t l_apic_timer_claim(irq_t *irq)
142{
143 return IRQ_ACCEPT;
144}
145
146static void l_apic_timer_irq_handler(irq_t *irq)
147{
148 /*
149 * Holding a spinlock could prevent clock() from preempting
150 * the current thread. In this case, we don't need to hold the
151 * irq->lock so we just unlock it and then lock it again.
152 */
153 irq_spinlock_unlock(&irq->lock, false);
154 clock();
155 irq_spinlock_lock(&irq->lock, false);
156}
157
158/** Get Local APIC ID.
159 *
160 * @return Local APIC ID.
161 *
162 */
163static uint8_t l_apic_id(void)
164{
165 l_apic_id_t idreg;
166
167 idreg.value = l_apic[L_APIC_ID];
168 return idreg.apic_id;
169}
170
171/** Initialize APIC on BSP. */
172void apic_init(void)
173{
174 exc_register(VECTOR_APIC_SPUR, "apic_spurious", false,
175 (iroutine_t) apic_spurious);
176
177 enable_irqs_function = io_apic_enable_irqs;
178 disable_irqs_function = io_apic_disable_irqs;
179 eoi_function = l_apic_eoi;
180 irqs_info = "apic";
181
182 /*
183 * Configure interrupt routing.
184 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
185 * Other interrupts will be forwarded to the lowest priority CPU.
186 */
187 io_apic_disable_irqs(0xffffU);
188
189 irq_initialize(&l_apic_timer_irq);
190 l_apic_timer_irq.preack = true;
191 l_apic_timer_irq.devno = device_assign_devno();
192 l_apic_timer_irq.inr = IRQ_CLK;
193 l_apic_timer_irq.claim = l_apic_timer_claim;
194 l_apic_timer_irq.handler = l_apic_timer_irq_handler;
195 irq_register(&l_apic_timer_irq);
196
197 uint8_t i;
198 for (i = 0; i < IRQ_COUNT; i++) {
199 int pin;
200
201 if ((pin = smp_irq_to_pin(i)) != -1)
202 io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI);
203 }
204
205 /*
206 * Ensure that io_apic has unique ID.
207 */
208 io_apic_id_t idreg;
209
210 idreg.value = io_apic_read(IOAPICID);
211 if ((1 << idreg.apic_id) & apic_id_mask) { /* See if IO APIC ID is used already */
212 for (i = 0; i < APIC_ID_COUNT; i++) {
213 if (!((1 << i) & apic_id_mask)) {
214 idreg.apic_id = i;
215 io_apic_write(IOAPICID, idreg.value);
216 break;
217 }
218 }
219 }
220
221 /*
222 * Configure the BSP's lapic.
223 */
224 l_apic_init();
225 l_apic_debug();
226
227 bsp_l_apic = l_apic_id();
228}
229
230/** Poll for APIC errors.
231 *
232 * Examine Error Status Register and report all errors found.
233 *
234 * @return 0 on error, 1 on success.
235 *
236 */
237int apic_poll_errors(void)
238{
239 esr_t esr;
240
241 esr.value = l_apic[ESR];
242
243 if (esr.send_checksum_error)
244 printf("Send Checksum Error\n");
245 if (esr.receive_checksum_error)
246 printf("Receive Checksum Error\n");
247 if (esr.send_accept_error)
248 printf("Send Accept Error\n");
249 if (esr.receive_accept_error)
250 printf("Receive Accept Error\n");
251 if (esr.send_illegal_vector)
252 printf("Send Illegal Vector\n");
253 if (esr.received_illegal_vector)
254 printf("Received Illegal Vector\n");
255 if (esr.illegal_register_address)
256 printf("Illegal Register Address\n");
257
258 return !esr.err_bitmap;
259}
260
261/* Waits for the destination cpu to accept the previous ipi. */
262static void l_apic_wait_for_delivery(void)
263{
264 icr_t icr;
265
266 do {
267 icr.lo = l_apic[ICRlo];
268 } while (icr.delivs != DELIVS_IDLE);
269}
270
271/** Send one CPU an IPI vector.
272 *
273 * @param apicid Physical APIC ID of the destination CPU.
274 * @param vector Interrupt vector to be sent.
275 *
276 * @return 0 on failure, 1 on success.
277 */
278int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
279{
280 icr_t icr;
281
282 /* Wait for a destination cpu to accept our previous ipi. */
283 l_apic_wait_for_delivery();
284
285 icr.lo = l_apic[ICRlo];
286 icr.hi = l_apic[ICRhi];
287
288 icr.delmod = DELMOD_FIXED;
289 icr.destmod = DESTMOD_PHYS;
290 icr.level = LEVEL_ASSERT;
291 icr.shorthand = SHORTHAND_NONE;
292 icr.trigger_mode = TRIGMOD_LEVEL;
293 icr.vector = vector;
294 icr.dest = apicid;
295
296 /* Send the IPI by writing to l_apic[ICRlo]. */
297 l_apic[ICRhi] = icr.hi;
298 l_apic[ICRlo] = icr.lo;
299
300 return apic_poll_errors();
301}
302
303/** Send all CPUs excluding CPU IPI vector.
304 *
305 * @param vector Interrupt vector to be sent.
306 *
307 * @return 0 on failure, 1 on success.
308 *
309 */
310int l_apic_broadcast_custom_ipi(uint8_t vector)
311{
312 icr_t icr;
313
314 /* Wait for a destination cpu to accept our previous ipi. */
315 l_apic_wait_for_delivery();
316
317 icr.lo = l_apic[ICRlo];
318 icr.delmod = DELMOD_FIXED;
319 icr.destmod = DESTMOD_LOGIC;
320 icr.level = LEVEL_ASSERT;
321 icr.shorthand = SHORTHAND_ALL_EXCL;
322 icr.trigger_mode = TRIGMOD_LEVEL;
323 icr.vector = vector;
324
325 l_apic[ICRlo] = icr.lo;
326
327 return apic_poll_errors();
328}
329
330/** Universal Start-up Algorithm for bringing up the AP processors.
331 *
332 * @param apicid APIC ID of the processor to be brought up.
333 *
334 * @return 0 on failure, 1 on success.
335 *
336 */
337int l_apic_send_init_ipi(uint8_t apicid)
338{
339 /*
340 * Read the ICR register in and zero all non-reserved fields.
341 */
342 icr_t icr;
343
344 icr.lo = l_apic[ICRlo];
345 icr.hi = l_apic[ICRhi];
346
347 icr.delmod = DELMOD_INIT;
348 icr.destmod = DESTMOD_PHYS;
349 icr.level = LEVEL_ASSERT;
350 icr.trigger_mode = TRIGMOD_LEVEL;
351 icr.shorthand = SHORTHAND_NONE;
352 icr.vector = 0;
353 icr.dest = apicid;
354
355 l_apic[ICRhi] = icr.hi;
356 l_apic[ICRlo] = icr.lo;
357
358 /*
359 * According to MP Specification, 20us should be enough to
360 * deliver the IPI.
361 */
362 delay(20);
363
364 if (!apic_poll_errors())
365 return 0;
366
367 l_apic_wait_for_delivery();
368
369 icr.lo = l_apic[ICRlo];
370 icr.delmod = DELMOD_INIT;
371 icr.destmod = DESTMOD_PHYS;
372 icr.level = LEVEL_DEASSERT;
373 icr.shorthand = SHORTHAND_NONE;
374 icr.trigger_mode = TRIGMOD_LEVEL;
375 icr.vector = 0;
376 l_apic[ICRlo] = icr.lo;
377
378 /*
379 * Wait 10ms as MP Specification specifies.
380 */
381 delay(10000);
382
383 if (!is_82489DX_apic(l_apic[LAVR])) {
384 /*
385 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
386 */
387 unsigned int i;
388 for (i = 0; i < 2; i++) {
389 icr.lo = l_apic[ICRlo];
390 icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */
391 icr.delmod = DELMOD_STARTUP;
392 icr.destmod = DESTMOD_PHYS;
393 icr.level = LEVEL_ASSERT;
394 icr.shorthand = SHORTHAND_NONE;
395 icr.trigger_mode = TRIGMOD_LEVEL;
396 l_apic[ICRlo] = icr.lo;
397 delay(200);
398 }
399 }
400
401 return apic_poll_errors();
402}
403
404/** Initialize Local APIC. */
405void l_apic_init(void)
406{
407 /* Initialize LVT Error register. */
408 lvt_error_t error;
409
410 error.value = l_apic[LVT_Err];
411 error.masked = true;
412 l_apic[LVT_Err] = error.value;
413
414 /* Initialize LVT LINT0 register. */
415 lvt_lint_t lint;
416
417 lint.value = l_apic[LVT_LINT0];
418 lint.masked = true;
419 l_apic[LVT_LINT0] = lint.value;
420
421 /* Initialize LVT LINT1 register. */
422 lint.value = l_apic[LVT_LINT1];
423 lint.masked = true;
424 l_apic[LVT_LINT1] = lint.value;
425
426 /* Task Priority Register initialization. */
427 tpr_t tpr;
428
429 tpr.value = l_apic[TPR];
430 tpr.pri_sc = 0;
431 tpr.pri = 0;
432 l_apic[TPR] = tpr.value;
433
434 /* Spurious-Interrupt Vector Register initialization. */
435 svr_t svr;
436
437 svr.value = l_apic[SVR];
438 svr.vector = VECTOR_APIC_SPUR;
439 svr.lapic_enabled = true;
440 svr.focus_checking = true;
441 l_apic[SVR] = svr.value;
442
443 if (CPU->arch.family >= 6)
444 enable_l_apic_in_msr();
445
446 /* Interrupt Command Register initialization. */
447 icr_t icr;
448
449 icr.lo = l_apic[ICRlo];
450 icr.delmod = DELMOD_INIT;
451 icr.destmod = DESTMOD_PHYS;
452 icr.level = LEVEL_DEASSERT;
453 icr.shorthand = SHORTHAND_ALL_INCL;
454 icr.trigger_mode = TRIGMOD_LEVEL;
455 l_apic[ICRlo] = icr.lo;
456
457 /* Timer Divide Configuration Register initialization. */
458 tdcr_t tdcr;
459
460 tdcr.value = l_apic[TDCR];
461 tdcr.div_value = DIVIDE_1;
462 l_apic[TDCR] = tdcr.value;
463
464 /* Program local timer. */
465 lvt_tm_t tm;
466
467 tm.value = l_apic[LVT_Tm];
468 tm.vector = VECTOR_CLK;
469 tm.mode = TIMER_PERIODIC;
470 tm.masked = false;
471 l_apic[LVT_Tm] = tm.value;
472
473 /*
474 * Measure and configure the timer to generate timer
475 * interrupt with period 1s/HZ seconds.
476 */
477 uint32_t t1 = l_apic[CCRT];
478 l_apic[ICRT] = 0xffffffff;
479
480 while (l_apic[CCRT] == t1);
481
482 t1 = l_apic[CCRT];
483 delay(1000000 / HZ);
484 uint32_t t2 = l_apic[CCRT];
485
486 l_apic[ICRT] = t1 - t2;
487
488 /* Program Logical Destination Register. */
489 ASSERT(CPU->id < 8);
490 ldr_t ldr;
491
492 ldr.value = l_apic[LDR];
493 ldr.id = (uint8_t) (1 << CPU->id);
494 l_apic[LDR] = ldr.value;
495
496 /* Program Destination Format Register for Flat mode. */
497 dfr_t dfr;
498
499 dfr.value = l_apic[DFR];
500 dfr.model = MODEL_FLAT;
501 l_apic[DFR] = dfr.value;
502}
503
504/** Local APIC End of Interrupt. */
505void l_apic_eoi(void)
506{
507 l_apic[EOI] = 0;
508}
509
510/** Dump content of Local APIC registers. */
511void l_apic_debug(void)
512{
513#ifdef LAPIC_VERBOSE
514 printf("LVT on cpu%u, LAPIC ID: %" PRIu8 "\n",
515 CPU->id, l_apic_id());
516
517 lvt_tm_t tm;
518 tm.value = l_apic[LVT_Tm];
519 printf("LVT Tm: vector=%" PRIu8 ", %s, %s, %s\n",
520 tm.vector, delivs_str[tm.delivs], mask_str[tm.masked],
521 tm_mode_str[tm.mode]);
522
523 lvt_lint_t lint;
524 lint.value = l_apic[LVT_LINT0];
525 printf("LVT LINT0: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
526 tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
527 intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
528 mask_str[lint.masked]);
529
530 lint.value = l_apic[LVT_LINT1];
531 printf("LVT LINT1: vector=%" PRIu8 ", %s, %s, %s, irr=%u, %s, %s\n",
532 tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs],
533 intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode],
534 mask_str[lint.masked]);
535
536 lvt_error_t error;
537 error.value = l_apic[LVT_Err];
538 printf("LVT Err: vector=%" PRIu8 ", %s, %s\n", error.vector,
539 delivs_str[error.delivs], mask_str[error.masked]);
540#endif
541}
542
543/** Read from IO APIC register.
544 *
545 * @param address IO APIC register address.
546 *
547 * @return Content of the addressed IO APIC register.
548 *
549 */
550uint32_t io_apic_read(uint8_t address)
551{
552 io_regsel_t regsel;
553
554 regsel.value = io_apic[IOREGSEL];
555 regsel.reg_addr = address;
556 io_apic[IOREGSEL] = regsel.value;
557 return io_apic[IOWIN];
558}
559
560/** Write to IO APIC register.
561 *
562 * @param address IO APIC register address.
563 * @param val Content to be written to the addressed IO APIC register.
564 *
565 */
566void io_apic_write(uint8_t address, uint32_t val)
567{
568 io_regsel_t regsel;
569
570 regsel.value = io_apic[IOREGSEL];
571 regsel.reg_addr = address;
572 io_apic[IOREGSEL] = regsel.value;
573 io_apic[IOWIN] = val;
574}
575
576/** Change some attributes of one item in I/O Redirection Table.
577 *
578 * @param pin IO APIC pin number.
579 * @param dest Interrupt destination address.
580 * @param vec Interrupt vector to trigger.
581 * @param flags Flags.
582 *
583 */
584void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t vec,
585 unsigned int flags)
586{
587 unsigned int dlvr;
588
589 if (flags & LOPRI)
590 dlvr = DELMOD_LOWPRI;
591 else
592 dlvr = DELMOD_FIXED;
593
594 io_redirection_reg_t reg;
595 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
596 reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1));
597
598 reg.dest = dest;
599 reg.destmod = DESTMOD_LOGIC;
600 reg.trigger_mode = TRIGMOD_EDGE;
601 reg.intpol = POLARITY_HIGH;
602 reg.delmod = dlvr;
603 reg.intvec = vec;
604
605 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
606 io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi);
607}
608
609/** Mask IRQs in IO APIC.
610 *
611 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
612 *
613 */
614void io_apic_disable_irqs(uint16_t irqmask)
615{
616 unsigned int i;
617 for (i = 0; i < 16; i++) {
618 if (irqmask & (1 << i)) {
619 /*
620 * Mask the signal input in IO APIC if there is a
621 * mapping for the respective IRQ number.
622 */
623 int pin = smp_irq_to_pin(i);
624 if (pin != -1) {
625 io_redirection_reg_t reg;
626
627 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
628 reg.masked = true;
629 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
630 }
631
632 }
633 }
634}
635
636/** Unmask IRQs in IO APIC.
637 *
638 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
639 *
640 */
641void io_apic_enable_irqs(uint16_t irqmask)
642{
643 unsigned int i;
644 for (i = 0; i < 16; i++) {
645 if (irqmask & (1 << i)) {
646 /*
647 * Unmask the signal input in IO APIC if there is a
648 * mapping for the respective IRQ number.
649 */
650 int pin = smp_irq_to_pin(i);
651 if (pin != -1) {
652 io_redirection_reg_t reg;
653
654 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
655 reg.masked = false;
656 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
657 }
658
659 }
660 }
661}
662
663#endif /* CONFIG_SMP */
664
665/** @}
666 */
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