source: mainline/kernel/arch/ia32/src/smp/apic.c@ 4edd57fd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4edd57fd was 214ec25c, checked in by Martin Decky <martin@…>, 15 years ago

use unsigned integers for exception and interrupt numbers
  • Property mode set to 100644
File size: 14.3 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <typedefs.h>
36#include <arch/smp/apic.h>
37#include <arch/smp/ap.h>
38#include <arch/smp/mps.h>
39#include <arch/boot/boot.h>
40#include <mm/page.h>
41#include <time/delay.h>
42#include <interrupt.h>
43#include <arch/interrupt.h>
44#include <print.h>
45#include <arch/asm.h>
46#include <arch.h>
47#include <ddi/irq.h>
48#include <ddi/device.h>
49
50#ifdef CONFIG_SMP
51
52/*
53 * Advanced Programmable Interrupt Controller for SMP systems.
54 * Tested on:
55 * Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
56 * Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
57 * VMware Workstation 5.5 with 2 CPUs
58 * QEMU 0.8.0 with 2-15 CPUs
59 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
60 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
61 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
62 *
63 */
64
65/*
66 * These variables either stay configured as initilalized, or are changed by
67 * the MP configuration code.
68 *
69 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
70 * optimize the code too much and accesses to l_apic and io_apic, that must
71 * always be 32-bit, would use byte oriented instructions.
72 *
73 */
74volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
75volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
76
77uint32_t apic_id_mask = 0;
78static irq_t l_apic_timer_irq;
79
80static int apic_poll_errors(void);
81
82#ifdef LAPIC_VERBOSE
83static const char *delmod_str[] = {
84 "Fixed",
85 "Lowest Priority",
86 "SMI",
87 "Reserved",
88 "NMI",
89 "INIT",
90 "STARTUP",
91 "ExtInt"
92};
93
94static const char *destmod_str[] = {
95 "Physical",
96 "Logical"
97};
98
99static const char *trigmod_str[] = {
100 "Edge",
101 "Level"
102};
103
104static const char *mask_str[] = {
105 "Unmasked",
106 "Masked"
107};
108
109static const char *delivs_str[] = {
110 "Idle",
111 "Send Pending"
112};
113
114static const char *tm_mode_str[] = {
115 "One-shot",
116 "Periodic"
117};
118
119static const char *intpol_str[] = {
120 "Polarity High",
121 "Polarity Low"
122};
123#endif /* LAPIC_VERBOSE */
124
125/** APIC spurious interrupt handler.
126 *
127 * @param n Interrupt vector.
128 * @param istate Interrupted state.
129 *
130 */
131static void apic_spurious(unsigned int n __attribute__((unused)),
132 istate_t *istate __attribute__((unused)))
133{
134#ifdef CONFIG_DEBUG
135 printf("cpu%u: APIC spurious interrupt\n", CPU->id);
136#endif
137}
138
139static irq_ownership_t l_apic_timer_claim(irq_t *irq)
140{
141 return IRQ_ACCEPT;
142}
143
144static void l_apic_timer_irq_handler(irq_t *irq)
145{
146 /*
147 * Holding a spinlock could prevent clock() from preempting
148 * the current thread. In this case, we don't need to hold the
149 * irq->lock so we just unlock it and then lock it again.
150 */
151 irq_spinlock_unlock(&irq->lock, false);
152 clock();
153 irq_spinlock_lock(&irq->lock, false);
154}
155
156/** Initialize APIC on BSP. */
157void apic_init(void)
158{
159 exc_register(VECTOR_APIC_SPUR, "apic_spurious", false,
160 (iroutine_t) apic_spurious);
161
162 enable_irqs_function = io_apic_enable_irqs;
163 disable_irqs_function = io_apic_disable_irqs;
164 eoi_function = l_apic_eoi;
165
166 /*
167 * Configure interrupt routing.
168 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
169 * Other interrupts will be forwarded to the lowest priority CPU.
170 */
171 io_apic_disable_irqs(0xffff);
172
173 irq_initialize(&l_apic_timer_irq);
174 l_apic_timer_irq.preack = true;
175 l_apic_timer_irq.devno = device_assign_devno();
176 l_apic_timer_irq.inr = IRQ_CLK;
177 l_apic_timer_irq.claim = l_apic_timer_claim;
178 l_apic_timer_irq.handler = l_apic_timer_irq_handler;
179 irq_register(&l_apic_timer_irq);
180
181 uint8_t i;
182 for (i = 0; i < IRQ_COUNT; i++) {
183 int pin;
184
185 if ((pin = smp_irq_to_pin(i)) != -1)
186 io_apic_change_ioredtbl((uint8_t) pin, DEST_ALL, (uint8_t) (IVT_IRQBASE + i), LOPRI);
187 }
188
189 /*
190 * Ensure that io_apic has unique ID.
191 */
192 io_apic_id_t idreg;
193
194 idreg.value = io_apic_read(IOAPICID);
195 if ((1 << idreg.apic_id) & apic_id_mask) { /* See if IO APIC ID is used already */
196 for (i = 0; i < APIC_ID_COUNT; i++) {
197 if (!((1 << i) & apic_id_mask)) {
198 idreg.apic_id = i;
199 io_apic_write(IOAPICID, idreg.value);
200 break;
201 }
202 }
203 }
204
205 /*
206 * Configure the BSP's lapic.
207 */
208 l_apic_init();
209 l_apic_debug();
210}
211
212/** Poll for APIC errors.
213 *
214 * Examine Error Status Register and report all errors found.
215 *
216 * @return 0 on error, 1 on success.
217 *
218 */
219int apic_poll_errors(void)
220{
221 esr_t esr;
222
223 esr.value = l_apic[ESR];
224
225 if (esr.send_checksum_error)
226 printf("Send Checksum Error\n");
227 if (esr.receive_checksum_error)
228 printf("Receive Checksum Error\n");
229 if (esr.send_accept_error)
230 printf("Send Accept Error\n");
231 if (esr.receive_accept_error)
232 printf("Receive Accept Error\n");
233 if (esr.send_illegal_vector)
234 printf("Send Illegal Vector\n");
235 if (esr.received_illegal_vector)
236 printf("Received Illegal Vector\n");
237 if (esr.illegal_register_address)
238 printf("Illegal Register Address\n");
239
240 return !esr.err_bitmap;
241}
242
243/** Send all CPUs excluding CPU IPI vector.
244 *
245 * @param vector Interrupt vector to be sent.
246 *
247 * @return 0 on failure, 1 on success.
248 *
249 */
250int l_apic_broadcast_custom_ipi(uint8_t vector)
251{
252 icr_t icr;
253
254 icr.lo = l_apic[ICRlo];
255 icr.delmod = DELMOD_FIXED;
256 icr.destmod = DESTMOD_LOGIC;
257 icr.level = LEVEL_ASSERT;
258 icr.shorthand = SHORTHAND_ALL_EXCL;
259 icr.trigger_mode = TRIGMOD_LEVEL;
260 icr.vector = vector;
261
262 l_apic[ICRlo] = icr.lo;
263
264 icr.lo = l_apic[ICRlo];
265 if (icr.delivs == DELIVS_PENDING) {
266#ifdef CONFIG_DEBUG
267 printf("IPI is pending.\n");
268#endif
269 }
270
271 return apic_poll_errors();
272}
273
274/** Universal Start-up Algorithm for bringing up the AP processors.
275 *
276 * @param apicid APIC ID of the processor to be brought up.
277 *
278 * @return 0 on failure, 1 on success.
279 *
280 */
281int l_apic_send_init_ipi(uint8_t apicid)
282{
283 /*
284 * Read the ICR register in and zero all non-reserved fields.
285 */
286 icr_t icr;
287
288 icr.lo = l_apic[ICRlo];
289 icr.hi = l_apic[ICRhi];
290
291 icr.delmod = DELMOD_INIT;
292 icr.destmod = DESTMOD_PHYS;
293 icr.level = LEVEL_ASSERT;
294 icr.trigger_mode = TRIGMOD_LEVEL;
295 icr.shorthand = SHORTHAND_NONE;
296 icr.vector = 0;
297 icr.dest = apicid;
298
299 l_apic[ICRhi] = icr.hi;
300 l_apic[ICRlo] = icr.lo;
301
302 /*
303 * According to MP Specification, 20us should be enough to
304 * deliver the IPI.
305 */
306 delay(20);
307
308 if (!apic_poll_errors())
309 return 0;
310
311 icr.lo = l_apic[ICRlo];
312 if (icr.delivs == DELIVS_PENDING) {
313#ifdef CONFIG_DEBUG
314 printf("IPI is pending.\n");
315#endif
316 }
317
318 icr.delmod = DELMOD_INIT;
319 icr.destmod = DESTMOD_PHYS;
320 icr.level = LEVEL_DEASSERT;
321 icr.shorthand = SHORTHAND_NONE;
322 icr.trigger_mode = TRIGMOD_LEVEL;
323 icr.vector = 0;
324 l_apic[ICRlo] = icr.lo;
325
326 /*
327 * Wait 10ms as MP Specification specifies.
328 */
329 delay(10000);
330
331 if (!is_82489DX_apic(l_apic[LAVR])) {
332 /*
333 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
334 */
335 unsigned int i;
336 for (i = 0; i < 2; i++) {
337 icr.lo = l_apic[ICRlo];
338 icr.vector = (uint8_t) (((uintptr_t) ap_boot) >> 12); /* calculate the reset vector */
339 icr.delmod = DELMOD_STARTUP;
340 icr.destmod = DESTMOD_PHYS;
341 icr.level = LEVEL_ASSERT;
342 icr.shorthand = SHORTHAND_NONE;
343 icr.trigger_mode = TRIGMOD_LEVEL;
344 l_apic[ICRlo] = icr.lo;
345 delay(200);
346 }
347 }
348
349 return apic_poll_errors();
350}
351
352/** Initialize Local APIC. */
353void l_apic_init(void)
354{
355 /* Initialize LVT Error register. */
356 lvt_error_t error;
357
358 error.value = l_apic[LVT_Err];
359 error.masked = true;
360 l_apic[LVT_Err] = error.value;
361
362 /* Initialize LVT LINT0 register. */
363 lvt_lint_t lint;
364
365 lint.value = l_apic[LVT_LINT0];
366 lint.masked = true;
367 l_apic[LVT_LINT0] = lint.value;
368
369 /* Initialize LVT LINT1 register. */
370 lint.value = l_apic[LVT_LINT1];
371 lint.masked = true;
372 l_apic[LVT_LINT1] = lint.value;
373
374 /* Task Priority Register initialization. */
375 tpr_t tpr;
376
377 tpr.value = l_apic[TPR];
378 tpr.pri_sc = 0;
379 tpr.pri = 0;
380 l_apic[TPR] = tpr.value;
381
382 /* Spurious-Interrupt Vector Register initialization. */
383 svr_t svr;
384
385 svr.value = l_apic[SVR];
386 svr.vector = VECTOR_APIC_SPUR;
387 svr.lapic_enabled = true;
388 svr.focus_checking = true;
389 l_apic[SVR] = svr.value;
390
391 if (CPU->arch.family >= 6)
392 enable_l_apic_in_msr();
393
394 /* Interrupt Command Register initialization. */
395 icr_t icr;
396
397 icr.lo = l_apic[ICRlo];
398 icr.delmod = DELMOD_INIT;
399 icr.destmod = DESTMOD_PHYS;
400 icr.level = LEVEL_DEASSERT;
401 icr.shorthand = SHORTHAND_ALL_INCL;
402 icr.trigger_mode = TRIGMOD_LEVEL;
403 l_apic[ICRlo] = icr.lo;
404
405 /* Timer Divide Configuration Register initialization. */
406 tdcr_t tdcr;
407
408 tdcr.value = l_apic[TDCR];
409 tdcr.div_value = DIVIDE_1;
410 l_apic[TDCR] = tdcr.value;
411
412 /* Program local timer. */
413 lvt_tm_t tm;
414
415 tm.value = l_apic[LVT_Tm];
416 tm.vector = VECTOR_CLK;
417 tm.mode = TIMER_PERIODIC;
418 tm.masked = false;
419 l_apic[LVT_Tm] = tm.value;
420
421 /*
422 * Measure and configure the timer to generate timer
423 * interrupt with period 1s/HZ seconds.
424 */
425 uint32_t t1 = l_apic[CCRT];
426 l_apic[ICRT] = 0xffffffff;
427
428 while (l_apic[CCRT] == t1);
429
430 t1 = l_apic[CCRT];
431 delay(1000000 / HZ);
432 uint32_t t2 = l_apic[CCRT];
433
434 l_apic[ICRT] = t1 - t2;
435
436 /* Program Logical Destination Register. */
437 ASSERT(CPU->id < 8);
438 ldr_t ldr;
439
440 ldr.value = l_apic[LDR];
441 ldr.id = (uint8_t) (1 << CPU->id);
442 l_apic[LDR] = ldr.value;
443
444 /* Program Destination Format Register for Flat mode. */
445 dfr_t dfr;
446
447 dfr.value = l_apic[DFR];
448 dfr.model = MODEL_FLAT;
449 l_apic[DFR] = dfr.value;
450}
451
452/** Local APIC End of Interrupt. */
453void l_apic_eoi(void)
454{
455 l_apic[EOI] = 0;
456}
457
458/** Dump content of Local APIC registers. */
459void l_apic_debug(void)
460{
461#ifdef LAPIC_VERBOSE
462 printf("LVT on cpu%" PRIs ", LAPIC ID: %" PRIu8 "\n", CPU->id, l_apic_id());
463
464 lvt_tm_t tm;
465 tm.value = l_apic[LVT_Tm];
466 printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
467
468 lvt_lint_t lint;
469 lint.value = l_apic[LVT_LINT0];
470 printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
471 lint.value = l_apic[LVT_LINT1];
472 printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
473
474 lvt_error_t error;
475 error.value = l_apic[LVT_Err];
476 printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
477#endif
478}
479
480/** Get Local APIC ID.
481 *
482 * @return Local APIC ID.
483 *
484 */
485uint8_t l_apic_id(void)
486{
487 l_apic_id_t idreg;
488
489 idreg.value = l_apic[L_APIC_ID];
490 return idreg.apic_id;
491}
492
493/** Read from IO APIC register.
494 *
495 * @param address IO APIC register address.
496 *
497 * @return Content of the addressed IO APIC register.
498 *
499 */
500uint32_t io_apic_read(uint8_t address)
501{
502 io_regsel_t regsel;
503
504 regsel.value = io_apic[IOREGSEL];
505 regsel.reg_addr = address;
506 io_apic[IOREGSEL] = regsel.value;
507 return io_apic[IOWIN];
508}
509
510/** Write to IO APIC register.
511 *
512 * @param address IO APIC register address.
513 * @param val Content to be written to the addressed IO APIC register.
514 *
515 */
516void io_apic_write(uint8_t address, uint32_t val)
517{
518 io_regsel_t regsel;
519
520 regsel.value = io_apic[IOREGSEL];
521 regsel.reg_addr = address;
522 io_apic[IOREGSEL] = regsel.value;
523 io_apic[IOWIN] = val;
524}
525
526/** Change some attributes of one item in I/O Redirection Table.
527 *
528 * @param pin IO APIC pin number.
529 * @param dest Interrupt destination address.
530 * @param vec Interrupt vector to trigger.
531 * @param flags Flags.
532 *
533 */
534void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t vec,
535 unsigned int flags)
536{
537 unsigned int dlvr;
538
539 if (flags & LOPRI)
540 dlvr = DELMOD_LOWPRI;
541 else
542 dlvr = DELMOD_FIXED;
543
544 io_redirection_reg_t reg;
545 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
546 reg.hi = io_apic_read((uint8_t) (IOREDTBL + pin * 2 + 1));
547
548 reg.dest = dest;
549 reg.destmod = DESTMOD_LOGIC;
550 reg.trigger_mode = TRIGMOD_EDGE;
551 reg.intpol = POLARITY_HIGH;
552 reg.delmod = dlvr;
553 reg.intvec = vec;
554
555 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
556 io_apic_write((uint8_t) (IOREDTBL + pin * 2 + 1), reg.hi);
557}
558
559/** Mask IRQs in IO APIC.
560 *
561 * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
562 *
563 */
564void io_apic_disable_irqs(uint16_t irqmask)
565{
566 unsigned int i;
567 for (i = 0; i < 16; i++) {
568 if (irqmask & (1 << i)) {
569 /*
570 * Mask the signal input in IO APIC if there is a
571 * mapping for the respective IRQ number.
572 */
573 int pin = smp_irq_to_pin(i);
574 if (pin != -1) {
575 io_redirection_reg_t reg;
576
577 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
578 reg.masked = true;
579 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
580 }
581
582 }
583 }
584}
585
586/** Unmask IRQs in IO APIC.
587 *
588 * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
589 *
590 */
591void io_apic_enable_irqs(uint16_t irqmask)
592{
593 unsigned int i;
594 for (i = 0; i < 16; i++) {
595 if (irqmask & (1 << i)) {
596 /*
597 * Unmask the signal input in IO APIC if there is a
598 * mapping for the respective IRQ number.
599 */
600 int pin = smp_irq_to_pin(i);
601 if (pin != -1) {
602 io_redirection_reg_t reg;
603
604 reg.lo = io_apic_read((uint8_t) (IOREDTBL + pin * 2));
605 reg.masked = false;
606 io_apic_write((uint8_t) (IOREDTBL + pin * 2), reg.lo);
607 }
608
609 }
610 }
611}
612
613#endif /* CONFIG_SMP */
614
615/** @}
616 */
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