source: mainline/kernel/arch/ia32/src/pm.c@ 7852625

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7852625 was ff586e06, checked in by Martin Decky <martin@…>, 15 years ago

indentation and spacing fixes (no change in functionality)
  • Property mode set to 100644
File size: 8.8 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/pm.h>
36#include <config.h>
37#include <typedefs.h>
38#include <arch/interrupt.h>
39#include <arch/asm.h>
40#include <arch/context.h>
41#include <panic.h>
42#include <arch/mm/page.h>
43#include <mm/slab.h>
44#include <memstr.h>
45#include <arch/boot/boot.h>
46#include <interrupt.h>
47
48/*
49 * Early ia32 configuration functions and data structures.
50 */
51
52/*
53 * We have no use for segmentation so we set up flat mode. In this
54 * mode, we use, for each privilege level, two segments spanning the
55 * whole memory. One is for code and one is for data.
56 *
57 * One is for GS register which holds pointer to the TLS thread
58 * structure in it's base.
59 */
60descriptor_t gdt[GDT_ITEMS] = {
61 /* NULL descriptor */
62 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
63 /* KTEXT descriptor */
64 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
65 /* KDATA descriptor */
66 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
67 /* UTEXT descriptor */
68 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
69 /* UDATA descriptor */
70 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
71 /* TSS descriptor - set up will be completed later */
72 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
73 /* TLS descriptor */
74 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
75 /* VESA Init descriptor */
76#ifdef CONFIG_FB
77 { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
78#endif
79};
80
81static idescriptor_t idt[IDT_ITEMS];
82
83static tss_t tss;
84
85tss_t *tss_p = NULL;
86
87/* gdtr is changed by kmp before next CPU is initialized */
88ptr_16_32_t gdtr = {
89 .limit = sizeof(gdt),
90 .base = (uintptr_t) gdt
91};
92
93void gdt_setbase(descriptor_t *d, uintptr_t base)
94{
95 d->base_0_15 = base & 0xffff;
96 d->base_16_23 = ((base) >> 16) & 0xff;
97 d->base_24_31 = ((base) >> 24) & 0xff;
98}
99
100void gdt_setlimit(descriptor_t *d, uint32_t limit)
101{
102 d->limit_0_15 = limit & 0xffff;
103 d->limit_16_19 = (limit >> 16) & 0xf;
104}
105
106void idt_setoffset(idescriptor_t *d, uintptr_t offset)
107{
108 /*
109 * Offset is a linear address.
110 */
111 d->offset_0_15 = offset & 0xffff;
112 d->offset_16_31 = offset >> 16;
113}
114
115void tss_initialize(tss_t *t)
116{
117 memsetb(t, sizeof(tss_t), 0);
118}
119
120/*
121 * This function takes care of proper setup of IDT and IDTR.
122 */
123void idt_init(void)
124{
125 idescriptor_t *d;
126 unsigned int i;
127
128 for (i = 0; i < IDT_ITEMS; i++) {
129 d = &idt[i];
130
131 d->unused = 0;
132 d->selector = GDT_SELECTOR(KTEXT_DES);
133
134 if (i == VECTOR_SYSCALL) {
135 /*
136 * The syscall trap gate must be callable from
137 * userland. Interrupts will remain enabled.
138 */
139 d->access = AR_PRESENT | AR_TRAP | DPL_USER;
140 } else {
141 /*
142 * Other interrupts use interrupt gates which
143 * disable interrupts.
144 */
145 d->access = AR_PRESENT | AR_INTERRUPT;
146 }
147 }
148
149 d = &idt[0];
150 idt_setoffset(d++, (uintptr_t) &int_0);
151 idt_setoffset(d++, (uintptr_t) &int_1);
152 idt_setoffset(d++, (uintptr_t) &int_2);
153 idt_setoffset(d++, (uintptr_t) &int_3);
154 idt_setoffset(d++, (uintptr_t) &int_4);
155 idt_setoffset(d++, (uintptr_t) &int_5);
156 idt_setoffset(d++, (uintptr_t) &int_6);
157 idt_setoffset(d++, (uintptr_t) &int_7);
158 idt_setoffset(d++, (uintptr_t) &int_8);
159 idt_setoffset(d++, (uintptr_t) &int_9);
160 idt_setoffset(d++, (uintptr_t) &int_10);
161 idt_setoffset(d++, (uintptr_t) &int_11);
162 idt_setoffset(d++, (uintptr_t) &int_12);
163 idt_setoffset(d++, (uintptr_t) &int_13);
164 idt_setoffset(d++, (uintptr_t) &int_14);
165 idt_setoffset(d++, (uintptr_t) &int_15);
166 idt_setoffset(d++, (uintptr_t) &int_16);
167 idt_setoffset(d++, (uintptr_t) &int_17);
168 idt_setoffset(d++, (uintptr_t) &int_18);
169 idt_setoffset(d++, (uintptr_t) &int_19);
170 idt_setoffset(d++, (uintptr_t) &int_20);
171 idt_setoffset(d++, (uintptr_t) &int_21);
172 idt_setoffset(d++, (uintptr_t) &int_22);
173 idt_setoffset(d++, (uintptr_t) &int_23);
174 idt_setoffset(d++, (uintptr_t) &int_24);
175 idt_setoffset(d++, (uintptr_t) &int_25);
176 idt_setoffset(d++, (uintptr_t) &int_26);
177 idt_setoffset(d++, (uintptr_t) &int_27);
178 idt_setoffset(d++, (uintptr_t) &int_28);
179 idt_setoffset(d++, (uintptr_t) &int_29);
180 idt_setoffset(d++, (uintptr_t) &int_30);
181 idt_setoffset(d++, (uintptr_t) &int_31);
182 idt_setoffset(d++, (uintptr_t) &int_32);
183 idt_setoffset(d++, (uintptr_t) &int_33);
184 idt_setoffset(d++, (uintptr_t) &int_34);
185 idt_setoffset(d++, (uintptr_t) &int_35);
186 idt_setoffset(d++, (uintptr_t) &int_36);
187 idt_setoffset(d++, (uintptr_t) &int_37);
188 idt_setoffset(d++, (uintptr_t) &int_38);
189 idt_setoffset(d++, (uintptr_t) &int_39);
190 idt_setoffset(d++, (uintptr_t) &int_40);
191 idt_setoffset(d++, (uintptr_t) &int_41);
192 idt_setoffset(d++, (uintptr_t) &int_42);
193 idt_setoffset(d++, (uintptr_t) &int_43);
194 idt_setoffset(d++, (uintptr_t) &int_44);
195 idt_setoffset(d++, (uintptr_t) &int_45);
196 idt_setoffset(d++, (uintptr_t) &int_46);
197 idt_setoffset(d++, (uintptr_t) &int_47);
198 idt_setoffset(d++, (uintptr_t) &int_48);
199 idt_setoffset(d++, (uintptr_t) &int_49);
200 idt_setoffset(d++, (uintptr_t) &int_50);
201 idt_setoffset(d++, (uintptr_t) &int_51);
202 idt_setoffset(d++, (uintptr_t) &int_52);
203 idt_setoffset(d++, (uintptr_t) &int_53);
204 idt_setoffset(d++, (uintptr_t) &int_54);
205 idt_setoffset(d++, (uintptr_t) &int_55);
206 idt_setoffset(d++, (uintptr_t) &int_56);
207 idt_setoffset(d++, (uintptr_t) &int_57);
208 idt_setoffset(d++, (uintptr_t) &int_58);
209 idt_setoffset(d++, (uintptr_t) &int_59);
210 idt_setoffset(d++, (uintptr_t) &int_60);
211 idt_setoffset(d++, (uintptr_t) &int_61);
212 idt_setoffset(d++, (uintptr_t) &int_62);
213 idt_setoffset(d++, (uintptr_t) &int_63);
214
215 idt_setoffset(&idt[VECTOR_SYSCALL], (uintptr_t) &int_syscall);
216}
217
218/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
219static void clean_IOPL_NT_flags(void)
220{
221 asm volatile (
222 "pushfl\n"
223 "pop %%eax\n"
224 "and $0xffff8fff, %%eax\n"
225 "push %%eax\n"
226 "popfl\n"
227 ::: "eax"
228 );
229}
230
231/* Clean AM(18) flag in CR0 register */
232static void clean_AM_flag(void)
233{
234 asm volatile (
235 "mov %%cr0, %%eax\n"
236 "and $0xfffbffff, %%eax\n"
237 "mov %%eax, %%cr0\n"
238 ::: "eax"
239 );
240}
241
242void pm_init(void)
243{
244 descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
245 ptr_16_32_t idtr;
246
247 /*
248 * Update addresses in GDT and IDT to their virtual counterparts.
249 */
250 idtr.limit = sizeof(idt);
251 idtr.base = (uintptr_t) idt;
252 gdtr_load(&gdtr);
253 idtr_load(&idtr);
254
255 /*
256 * Each CPU has its private GDT and TSS.
257 * All CPUs share one IDT.
258 */
259
260 if (config.cpu_active == 1) {
261 idt_init();
262 /*
263 * NOTE: bootstrap CPU has statically allocated TSS, because
264 * the heap hasn't been initialized so far.
265 */
266 tss_p = &tss;
267 }
268 else {
269 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
270 if (!tss_p)
271 panic("Cannot allocate TSS.");
272 }
273
274 tss_initialize(tss_p);
275
276 gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
277 gdt_p[TSS_DES].special = 1;
278 gdt_p[TSS_DES].granularity = 0;
279
280 gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
281 gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
282
283 /*
284 * As of this moment, the current CPU has its own GDT pointing
285 * to its own TSS. We just need to load the TR register.
286 */
287 tr_load(GDT_SELECTOR(TSS_DES));
288
289 clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
290 clean_AM_flag(); /* Disable alignment check */
291}
292
293void set_tls_desc(uintptr_t tls)
294{
295 ptr_16_32_t cpugdtr;
296 descriptor_t *gdt_p;
297
298 gdtr_store(&cpugdtr);
299 gdt_p = (descriptor_t *) cpugdtr.base;
300 gdt_setbase(&gdt_p[TLS_DES], tls);
301 /* Reload gdt register to update GS in CPU */
302 gdtr_load(&cpugdtr);
303}
304
305/** @}
306 */
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