| 1 | /*
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| 2 | * Copyright (c) 2001-2004 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup kernel_ia32
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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| 35 | #include <arch/pm.h>
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| 36 | #include <config.h>
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| 37 | #include <typedefs.h>
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| 38 | #include <arch/interrupt.h>
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| 39 | #include <arch/asm.h>
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| 40 | #include <arch/context.h>
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| 41 | #include <panic.h>
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| 42 | #include <arch/mm/page.h>
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| 43 | #include <mm/km.h>
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| 44 | #include <mm/frame.h>
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| 45 | #include <stdlib.h>
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| 46 | #include <mem.h>
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| 47 | #include <arch/boot/boot.h>
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| 48 | #include <interrupt.h>
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| 49 | #include <arch/cpu.h>
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| 50 |
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| 51 | /*
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| 52 | * Early ia32 configuration functions and data structures.
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| 53 | */
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| 54 |
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| 55 | /*
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| 56 | * We don't have much use for segmentation so we set up flat mode.
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| 57 | * In this mode, we use, for each privilege level, two segments spanning the
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| 58 | * whole memory. One is for code and one is for data.
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| 59 | *
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| 60 | * One special segment apart of that is for the GS register which holds
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| 61 | * a pointer to the VREG page in its base.
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| 62 | */
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| 63 | descriptor_t gdt[GDT_ITEMS] = {
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| 64 | [NULL_DES] = {
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| 65 | 0
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| 66 | },
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| 67 | [KTEXT_DES] = {
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| 68 | .limit_0_15 = 0xffff,
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| 69 | .limit_16_19 = 0xf,
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| 70 | .access = AR_PRESENT | AR_CODE | DPL_KERNEL,
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| 71 | .special = 1,
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| 72 | .granularity = 1
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| 73 | },
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| 74 | [KDATA_DES] = {
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| 75 | .limit_0_15 = 0xffff,
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| 76 | .limit_16_19 = 0xf,
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| 77 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
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| 78 | .special = 1,
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| 79 | .granularity = 1
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| 80 | },
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| 81 | [UTEXT_DES] = {
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| 82 | .limit_0_15 = 0xffff,
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| 83 | .limit_16_19 = 0xf,
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| 84 | .access = AR_PRESENT | AR_CODE | DPL_USER,
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| 85 | .special = 1,
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| 86 | .granularity = 1
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| 87 | },
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| 88 | [UDATA_DES] = {
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| 89 | .limit_0_15 = 0xffff,
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| 90 | .limit_16_19 = 0xf,
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| 91 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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| 92 | .special = 1,
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| 93 | .granularity = 1
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| 94 | },
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| 95 | [TSS_DES] = { /* set up will be completed later */
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| 96 | 0,
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| 97 | },
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| 98 | [VREG_DES] = { /* will be reinitialized later */
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| 99 | .limit_0_15 = 0xffff,
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| 100 | .limit_16_19 = 0xf,
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| 101 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
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| 102 | .special = 1,
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| 103 | .granularity = 1
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| 104 | },
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| 105 | /* VESA Init descriptor */
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| 106 | #ifdef CONFIG_FB
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| 107 | [VESA_INIT_CODE_DES] = {
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| 108 | .limit_0_15 = 0xffff,
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| 109 | .limit_16_19 = 0xf,
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| 110 | .base_16_23 = VESA_INIT_SEGMENT >> 12,
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| 111 | .access = AR_PRESENT | AR_CODE | AR_READABLE | DPL_KERNEL
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| 112 | },
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| 113 | [VESA_INIT_DATA_DES] = {
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| 114 | .limit_0_15 = 0xffff,
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| 115 | .limit_16_19 = 0xf,
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| 116 | .base_16_23 = VESA_INIT_SEGMENT >> 12,
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| 117 | .access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL
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| 118 | }
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| 119 | #endif
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| 120 | };
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| 121 |
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| 122 | static idescriptor_t idt[IDT_ITEMS];
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| 123 |
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| 124 | static tss_t tss0;
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| 125 |
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| 126 | tss_t *tss_p = NULL;
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| 127 |
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| 128 | /* gdtr is changed by kmp before next CPU is initialized */
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| 129 | ptr_16_32_t gdtr = {
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| 130 | .limit = sizeof(gdt),
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| 131 | .base = (uintptr_t) gdt
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| 132 | };
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| 133 |
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| 134 | void gdt_setbase(descriptor_t *d, uintptr_t base)
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| 135 | {
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| 136 | d->base_0_15 = base & 0xffff;
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| 137 | d->base_16_23 = (base >> 16) & 0xff;
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| 138 | d->base_24_31 = (base >> 24) & 0xff;
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| 139 | }
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| 140 |
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| 141 | void gdt_setlimit(descriptor_t *d, uint32_t limit)
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| 142 | {
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| 143 | d->limit_0_15 = limit & 0xffff;
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| 144 | d->limit_16_19 = (limit >> 16) & 0xf;
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| 145 | }
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| 146 |
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| 147 | void idt_setoffset(idescriptor_t *d, uintptr_t offset)
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| 148 | {
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| 149 | /*
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| 150 | * Offset is a linear address.
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| 151 | */
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| 152 | d->offset_0_15 = offset & 0xffff;
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| 153 | d->offset_16_31 = offset >> 16;
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| 154 | }
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| 155 |
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| 156 | void tss_initialize(tss_t *t)
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| 157 | {
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| 158 | memsetb(t, sizeof(tss_t), 0);
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| 159 | }
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| 160 |
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| 161 | /*
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| 162 | * This function takes care of proper setup of IDT and IDTR.
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| 163 | */
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| 164 | void idt_init(void)
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| 165 | {
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| 166 | idescriptor_t *d;
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| 167 | unsigned int i;
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| 168 |
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| 169 | for (i = 0; i < IDT_ITEMS; i++) {
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| 170 | d = &idt[i];
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| 171 |
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| 172 | d->unused = 0;
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| 173 | d->selector = GDT_SELECTOR(KTEXT_DES);
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| 174 |
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| 175 | if (i == VECTOR_SYSCALL) {
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| 176 | /*
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| 177 | * The syscall trap gate must be callable from
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| 178 | * userland. Interrupts will remain enabled.
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| 179 | */
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| 180 | d->access = AR_PRESENT | AR_TRAP | DPL_USER;
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| 181 | } else {
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| 182 | /*
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| 183 | * Other interrupts use interrupt gates which
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| 184 | * disable interrupts.
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| 185 | */
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| 186 | d->access = AR_PRESENT | AR_INTERRUPT;
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| 187 | }
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| 188 | }
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| 189 |
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| 190 | d = &idt[0];
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| 191 | idt_setoffset(d++, (uintptr_t) &int_0);
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| 192 | idt_setoffset(d++, (uintptr_t) &int_1);
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| 193 | idt_setoffset(d++, (uintptr_t) &int_2);
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| 194 | idt_setoffset(d++, (uintptr_t) &int_3);
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| 195 | idt_setoffset(d++, (uintptr_t) &int_4);
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| 196 | idt_setoffset(d++, (uintptr_t) &int_5);
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| 197 | idt_setoffset(d++, (uintptr_t) &int_6);
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| 198 | idt_setoffset(d++, (uintptr_t) &int_7);
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| 199 | idt_setoffset(d++, (uintptr_t) &int_8);
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| 200 | idt_setoffset(d++, (uintptr_t) &int_9);
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| 201 | idt_setoffset(d++, (uintptr_t) &int_10);
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| 202 | idt_setoffset(d++, (uintptr_t) &int_11);
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| 203 | idt_setoffset(d++, (uintptr_t) &int_12);
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| 204 | idt_setoffset(d++, (uintptr_t) &int_13);
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| 205 | idt_setoffset(d++, (uintptr_t) &int_14);
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| 206 | idt_setoffset(d++, (uintptr_t) &int_15);
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| 207 | idt_setoffset(d++, (uintptr_t) &int_16);
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| 208 | idt_setoffset(d++, (uintptr_t) &int_17);
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| 209 | idt_setoffset(d++, (uintptr_t) &int_18);
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| 210 | idt_setoffset(d++, (uintptr_t) &int_19);
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| 211 | idt_setoffset(d++, (uintptr_t) &int_20);
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| 212 | idt_setoffset(d++, (uintptr_t) &int_21);
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| 213 | idt_setoffset(d++, (uintptr_t) &int_22);
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| 214 | idt_setoffset(d++, (uintptr_t) &int_23);
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| 215 | idt_setoffset(d++, (uintptr_t) &int_24);
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| 216 | idt_setoffset(d++, (uintptr_t) &int_25);
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| 217 | idt_setoffset(d++, (uintptr_t) &int_26);
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| 218 | idt_setoffset(d++, (uintptr_t) &int_27);
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| 219 | idt_setoffset(d++, (uintptr_t) &int_28);
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| 220 | idt_setoffset(d++, (uintptr_t) &int_29);
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| 221 | idt_setoffset(d++, (uintptr_t) &int_30);
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| 222 | idt_setoffset(d++, (uintptr_t) &int_31);
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| 223 | idt_setoffset(d++, (uintptr_t) &int_32);
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| 224 | idt_setoffset(d++, (uintptr_t) &int_33);
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| 225 | idt_setoffset(d++, (uintptr_t) &int_34);
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| 226 | idt_setoffset(d++, (uintptr_t) &int_35);
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| 227 | idt_setoffset(d++, (uintptr_t) &int_36);
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| 228 | idt_setoffset(d++, (uintptr_t) &int_37);
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| 229 | idt_setoffset(d++, (uintptr_t) &int_38);
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| 230 | idt_setoffset(d++, (uintptr_t) &int_39);
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| 231 | idt_setoffset(d++, (uintptr_t) &int_40);
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| 232 | idt_setoffset(d++, (uintptr_t) &int_41);
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| 233 | idt_setoffset(d++, (uintptr_t) &int_42);
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| 234 | idt_setoffset(d++, (uintptr_t) &int_43);
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| 235 | idt_setoffset(d++, (uintptr_t) &int_44);
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| 236 | idt_setoffset(d++, (uintptr_t) &int_45);
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| 237 | idt_setoffset(d++, (uintptr_t) &int_46);
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| 238 | idt_setoffset(d++, (uintptr_t) &int_47);
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| 239 | idt_setoffset(d++, (uintptr_t) &int_48);
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| 240 | idt_setoffset(d++, (uintptr_t) &int_49);
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| 241 | idt_setoffset(d++, (uintptr_t) &int_50);
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| 242 | idt_setoffset(d++, (uintptr_t) &int_51);
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| 243 | idt_setoffset(d++, (uintptr_t) &int_52);
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| 244 | idt_setoffset(d++, (uintptr_t) &int_53);
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| 245 | idt_setoffset(d++, (uintptr_t) &int_54);
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| 246 | idt_setoffset(d++, (uintptr_t) &int_55);
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| 247 | idt_setoffset(d++, (uintptr_t) &int_56);
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| 248 | idt_setoffset(d++, (uintptr_t) &int_57);
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| 249 | idt_setoffset(d++, (uintptr_t) &int_58);
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| 250 | idt_setoffset(d++, (uintptr_t) &int_59);
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| 251 | idt_setoffset(d++, (uintptr_t) &int_60);
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| 252 | idt_setoffset(d++, (uintptr_t) &int_61);
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| 253 | idt_setoffset(d++, (uintptr_t) &int_62);
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| 254 | idt_setoffset(d++, (uintptr_t) &int_63);
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| 255 |
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| 256 | idt_setoffset(&idt[VECTOR_SYSCALL], (uintptr_t) &int_syscall);
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| 257 | }
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| 258 |
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| 259 | void pm_init(void)
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| 260 | {
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| 261 | descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
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| 262 | ptr_16_32_t idtr;
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| 263 |
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| 264 | /*
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| 265 | * Update addresses in GDT and IDT to their virtual counterparts.
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| 266 | */
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| 267 | idtr.limit = sizeof(idt);
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| 268 | idtr.base = (uintptr_t) idt;
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| 269 | gdtr_load(&gdtr);
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| 270 | idtr_load(&idtr);
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| 271 |
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| 272 | /*
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| 273 | * Each CPU has its private GDT and TSS.
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| 274 | * All CPUs share one IDT.
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| 275 | */
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| 276 |
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| 277 | if (config.cpu_active == 1) {
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| 278 | idt_init();
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| 279 | /*
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| 280 | * NOTE: bootstrap CPU has statically allocated TSS, because
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| 281 | * the heap hasn't been initialized so far.
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| 282 | */
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| 283 | tss_p = &tss0;
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| 284 | } else {
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| 285 | tss_p = (tss_t *) malloc(sizeof(tss_t));
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| 286 | if (!tss_p)
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| 287 | panic("Cannot allocate TSS.");
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| 288 | }
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| 289 |
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| 290 | tss_initialize(tss_p);
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| 291 |
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| 292 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
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| 293 | gdt_p[TSS_DES].special = 1;
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| 294 | gdt_p[TSS_DES].granularity = 0;
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| 295 |
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| 296 | gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
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| 297 | gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
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| 298 |
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| 299 | /*
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| 300 | * As of this moment, the current CPU has its own GDT pointing
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| 301 | * to its own TSS. We just need to load the TR register.
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| 302 | */
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| 303 | tr_load(GDT_SELECTOR(TSS_DES));
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| 304 |
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| 305 | /* Disable I/O on nonprivileged levels and clear NT flag. */
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| 306 | write_eflags(read_eflags() & ~(EFLAGS_IOPL | EFLAGS_NT));
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| 307 |
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| 308 | /* Disable alignment check */
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| 309 | write_cr0(read_cr0() & ~CR0_AM);
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| 310 | }
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| 311 |
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| 312 | /** @}
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| 313 | */
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