source: mainline/kernel/arch/ia32/src/pm.c@ be3f94c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since be3f94c was 1d3d2cf, checked in by Martin Decky <martin@…>, 15 years ago

rename gdtselector to GDT_SELECTOR to make explicit it is a macro
unify how bootstrap_gdtr is defined on amd64 and ia32
  • Property mode set to 100644
File size: 8.7 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/pm.h>
36#include <config.h>
37#include <typedefs.h>
38#include <arch/interrupt.h>
39#include <arch/asm.h>
40#include <arch/context.h>
41#include <panic.h>
42#include <arch/mm/page.h>
43#include <mm/slab.h>
44#include <memstr.h>
45#include <arch/boot/boot.h>
46#include <interrupt.h>
47
48/*
49 * Early ia32 configuration functions and data structures.
50 */
51
52/*
53 * We have no use for segmentation so we set up flat mode. In this
54 * mode, we use, for each privilege level, two segments spanning the
55 * whole memory. One is for code and one is for data.
56 *
57 * One is for GS register which holds pointer to the TLS thread
58 * structure in it's base.
59 */
60descriptor_t gdt[GDT_ITEMS] = {
61 /* NULL descriptor */
62 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
63 /* KTEXT descriptor */
64 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
65 /* KDATA descriptor */
66 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
67 /* UTEXT descriptor */
68 { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
69 /* UDATA descriptor */
70 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
71 /* TSS descriptor - set up will be completed later */
72 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
73 /* TLS descriptor */
74 { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
75 /* VESA Init descriptor */
76#ifdef CONFIG_FB
77 { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
78#endif
79};
80
81static idescriptor_t idt[IDT_ITEMS];
82
83static tss_t tss;
84
85tss_t *tss_p = NULL;
86
87/* gdtr is changed by kmp before next CPU is initialized */
88ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
89
90void gdt_setbase(descriptor_t *d, uintptr_t base)
91{
92 d->base_0_15 = base & 0xffff;
93 d->base_16_23 = ((base) >> 16) & 0xff;
94 d->base_24_31 = ((base) >> 24) & 0xff;
95}
96
97void gdt_setlimit(descriptor_t *d, uint32_t limit)
98{
99 d->limit_0_15 = limit & 0xffff;
100 d->limit_16_19 = (limit >> 16) & 0xf;
101}
102
103void idt_setoffset(idescriptor_t *d, uintptr_t offset)
104{
105 /*
106 * Offset is a linear address.
107 */
108 d->offset_0_15 = offset & 0xffff;
109 d->offset_16_31 = offset >> 16;
110}
111
112void tss_initialize(tss_t *t)
113{
114 memsetb(t, sizeof(tss_t), 0);
115}
116
117/*
118 * This function takes care of proper setup of IDT and IDTR.
119 */
120void idt_init(void)
121{
122 idescriptor_t *d;
123 unsigned int i;
124
125 for (i = 0; i < IDT_ITEMS; i++) {
126 d = &idt[i];
127
128 d->unused = 0;
129 d->selector = GDT_SELECTOR(KTEXT_DES);
130
131 if (i == VECTOR_SYSCALL) {
132 /*
133 * The syscall trap gate must be callable from
134 * userland. Interrupts will remain enabled.
135 */
136 d->access = AR_PRESENT | AR_TRAP | DPL_USER;
137 } else {
138 /*
139 * Other interrupts use interrupt gates which
140 * disable interrupts.
141 */
142 d->access = AR_PRESENT | AR_INTERRUPT;
143 }
144 }
145
146 d = &idt[0];
147 idt_setoffset(d++, (uintptr_t) &int_0);
148 idt_setoffset(d++, (uintptr_t) &int_1);
149 idt_setoffset(d++, (uintptr_t) &int_2);
150 idt_setoffset(d++, (uintptr_t) &int_3);
151 idt_setoffset(d++, (uintptr_t) &int_4);
152 idt_setoffset(d++, (uintptr_t) &int_5);
153 idt_setoffset(d++, (uintptr_t) &int_6);
154 idt_setoffset(d++, (uintptr_t) &int_7);
155 idt_setoffset(d++, (uintptr_t) &int_8);
156 idt_setoffset(d++, (uintptr_t) &int_9);
157 idt_setoffset(d++, (uintptr_t) &int_10);
158 idt_setoffset(d++, (uintptr_t) &int_11);
159 idt_setoffset(d++, (uintptr_t) &int_12);
160 idt_setoffset(d++, (uintptr_t) &int_13);
161 idt_setoffset(d++, (uintptr_t) &int_14);
162 idt_setoffset(d++, (uintptr_t) &int_15);
163 idt_setoffset(d++, (uintptr_t) &int_16);
164 idt_setoffset(d++, (uintptr_t) &int_17);
165 idt_setoffset(d++, (uintptr_t) &int_18);
166 idt_setoffset(d++, (uintptr_t) &int_19);
167 idt_setoffset(d++, (uintptr_t) &int_20);
168 idt_setoffset(d++, (uintptr_t) &int_21);
169 idt_setoffset(d++, (uintptr_t) &int_22);
170 idt_setoffset(d++, (uintptr_t) &int_23);
171 idt_setoffset(d++, (uintptr_t) &int_24);
172 idt_setoffset(d++, (uintptr_t) &int_25);
173 idt_setoffset(d++, (uintptr_t) &int_26);
174 idt_setoffset(d++, (uintptr_t) &int_27);
175 idt_setoffset(d++, (uintptr_t) &int_28);
176 idt_setoffset(d++, (uintptr_t) &int_29);
177 idt_setoffset(d++, (uintptr_t) &int_30);
178 idt_setoffset(d++, (uintptr_t) &int_31);
179 idt_setoffset(d++, (uintptr_t) &int_32);
180 idt_setoffset(d++, (uintptr_t) &int_33);
181 idt_setoffset(d++, (uintptr_t) &int_34);
182 idt_setoffset(d++, (uintptr_t) &int_35);
183 idt_setoffset(d++, (uintptr_t) &int_36);
184 idt_setoffset(d++, (uintptr_t) &int_37);
185 idt_setoffset(d++, (uintptr_t) &int_38);
186 idt_setoffset(d++, (uintptr_t) &int_39);
187 idt_setoffset(d++, (uintptr_t) &int_40);
188 idt_setoffset(d++, (uintptr_t) &int_41);
189 idt_setoffset(d++, (uintptr_t) &int_42);
190 idt_setoffset(d++, (uintptr_t) &int_43);
191 idt_setoffset(d++, (uintptr_t) &int_44);
192 idt_setoffset(d++, (uintptr_t) &int_45);
193 idt_setoffset(d++, (uintptr_t) &int_46);
194 idt_setoffset(d++, (uintptr_t) &int_47);
195 idt_setoffset(d++, (uintptr_t) &int_48);
196 idt_setoffset(d++, (uintptr_t) &int_49);
197 idt_setoffset(d++, (uintptr_t) &int_50);
198 idt_setoffset(d++, (uintptr_t) &int_51);
199 idt_setoffset(d++, (uintptr_t) &int_52);
200 idt_setoffset(d++, (uintptr_t) &int_53);
201 idt_setoffset(d++, (uintptr_t) &int_54);
202 idt_setoffset(d++, (uintptr_t) &int_55);
203 idt_setoffset(d++, (uintptr_t) &int_56);
204 idt_setoffset(d++, (uintptr_t) &int_57);
205 idt_setoffset(d++, (uintptr_t) &int_58);
206 idt_setoffset(d++, (uintptr_t) &int_59);
207 idt_setoffset(d++, (uintptr_t) &int_60);
208 idt_setoffset(d++, (uintptr_t) &int_61);
209 idt_setoffset(d++, (uintptr_t) &int_62);
210 idt_setoffset(d++, (uintptr_t) &int_63);
211
212 idt_setoffset(&idt[VECTOR_SYSCALL], (uintptr_t) &int_syscall);
213}
214
215/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
216static void clean_IOPL_NT_flags(void)
217{
218 asm volatile (
219 "pushfl\n"
220 "pop %%eax\n"
221 "and $0xffff8fff, %%eax\n"
222 "push %%eax\n"
223 "popfl\n"
224 ::: "eax"
225 );
226}
227
228/* Clean AM(18) flag in CR0 register */
229static void clean_AM_flag(void)
230{
231 asm volatile (
232 "mov %%cr0, %%eax\n"
233 "and $0xfffbffff, %%eax\n"
234 "mov %%eax, %%cr0\n"
235 ::: "eax"
236 );
237}
238
239void pm_init(void)
240{
241 descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
242 ptr_16_32_t idtr;
243
244 /*
245 * Update addresses in GDT and IDT to their virtual counterparts.
246 */
247 idtr.limit = sizeof(idt);
248 idtr.base = (uintptr_t) idt;
249 gdtr_load(&gdtr);
250 idtr_load(&idtr);
251
252 /*
253 * Each CPU has its private GDT and TSS.
254 * All CPUs share one IDT.
255 */
256
257 if (config.cpu_active == 1) {
258 idt_init();
259 /*
260 * NOTE: bootstrap CPU has statically allocated TSS, because
261 * the heap hasn't been initialized so far.
262 */
263 tss_p = &tss;
264 }
265 else {
266 tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
267 if (!tss_p)
268 panic("Cannot allocate TSS.");
269 }
270
271 tss_initialize(tss_p);
272
273 gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
274 gdt_p[TSS_DES].special = 1;
275 gdt_p[TSS_DES].granularity = 0;
276
277 gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
278 gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
279
280 /*
281 * As of this moment, the current CPU has its own GDT pointing
282 * to its own TSS. We just need to load the TR register.
283 */
284 tr_load(GDT_SELECTOR(TSS_DES));
285
286 clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
287 clean_AM_flag(); /* Disable alignment check */
288}
289
290void set_tls_desc(uintptr_t tls)
291{
292 ptr_16_32_t cpugdtr;
293 descriptor_t *gdt_p;
294
295 gdtr_store(&cpugdtr);
296 gdt_p = (descriptor_t *) cpugdtr.base;
297 gdt_setbase(&gdt_p[TLS_DES], tls);
298 /* Reload gdt register to update GS in CPU */
299 gdtr_load(&cpugdtr);
300}
301
302/** @}
303 */
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