source: mainline/kernel/arch/ia32/src/interrupt.c@ c46bfbc

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c46bfbc was 63e27ef, checked in by Jiri Svoboda <jiri@…>, 8 years ago

ASSERT → assert

  • Property mode set to 100644
File size: 7.1 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[b6529ae]29/** @addtogroup ia32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/interrupt.h>
[63e27ef]36#include <assert.h>
[204674e]37#include <syscall/syscall.h>
[f761f1eb]38#include <print.h>
[02a99d2]39#include <debug.h>
[f761f1eb]40#include <panic.h>
[80d31883]41#include <arch/drivers/i8259.h>
[f761f1eb]42#include <func.h>
43#include <cpu.h>
44#include <arch/asm.h>
[169587a]45#include <mm/tlb.h>
[20d50a1]46#include <mm/as.h>
[cb4b61d]47#include <arch.h>
[1084a784]48#include <proc/thread.h>
[2382d09]49#include <proc/task.h>
50#include <synch/spinlock.h>
51#include <arch/ddi/ddi.h>
[5626277]52#include <ipc/sysipc.h>
53#include <interrupt.h>
[cea12e9]54#include <ddi/irq.h>
[e2b762ec]55#include <symtab.h>
[203deeb8]56#include <stacktrace.h>
[2ee1ccc]57#include <smp/smp_call.h>
[1066041]58#include <proc/task.h>
[e2b762ec]59
[f761f1eb]60/*
61 * Interrupt and exception dispatching.
62 */
63
[7f1c620]64void (* disable_irqs_function)(uint16_t irqmask) = NULL;
65void (* enable_irqs_function)(uint16_t irqmask) = NULL;
[f761f1eb]66void (* eoi_function)(void) = NULL;
[acc7ce4]67const char *irqs_info = NULL;
[f761f1eb]68
[22a28a69]69void istate_decode(istate_t *istate)
[97b64c9]70{
[f36787d7]71 printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
72 "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
73 istate->cs, istate->eip, istate->eflags, istate->error_word);
[7e752b2]74
[f36787d7]75 printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
76 "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
[0d1e976]77 istate->ds, istate->es, istate->fs, istate->gs);
[7e752b2]78
[c9eb31c2]79 if (istate_from_uspace(istate))
[f36787d7]80 printf("ss =%0#10" PRIx32 "\n", istate->ss);
[7e752b2]81
[f36787d7]82 printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
83 "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
[0d1e976]84 istate->eax, istate->ebx, istate->ecx, istate->edx);
[7e752b2]85
[f36787d7]86 printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
87 "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
88 istate->esi, istate->edi, istate->ebp,
89 istate_from_uspace(istate) ? istate->esp :
90 (uintptr_t) &istate->esp);
[97b64c9]91}
[ab08b42]92
[cea12e9]93static void trap_virtual_eoi(void)
94{
95 if (eoi_function)
96 eoi_function();
97 else
[f651e80]98 panic("No eoi_function.");
[cea12e9]99
100}
101
[214ec25c]102static void null_interrupt(unsigned int n, istate_t *istate)
[f761f1eb]103{
[214ec25c]104 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
[62baed17]105 panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
[f761f1eb]106}
107
[214ec25c]108static void de_fault(unsigned int n, istate_t *istate)
[4491338]109{
110 fault_if_from_uspace(istate, "Divide error.");
[62baed17]111 panic_badtrap(istate, n, "Divide error.");
[4491338]112}
113
[2382d09]114/** General Protection Fault. */
[214ec25c]115static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[f761f1eb]116{
[2382d09]117 if (TASK) {
[da1bafb]118 irq_spinlock_lock(&TASK->lock, false);
119 size_t ver = TASK->arch.iomapver;
120 irq_spinlock_unlock(&TASK->lock, false);
[2382d09]121
122 if (CPU->arch.iomapver_copy != ver) {
123 /*
124 * This fault can be caused by an early access
125 * to I/O port because of an out-dated
126 * I/O Permission bitmap installed on CPU.
127 * Install the fresh copy and restart
128 * the instruction.
129 */
130 io_perm_bitmap_install();
131 return;
132 }
[f651e80]133 fault_if_from_uspace(istate, "General protection fault.");
[2382d09]134 }
[62baed17]135 panic_badtrap(istate, n, "General protection fault.");
[f761f1eb]136}
137
[214ec25c]138static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[6de2480e]139{
[f651e80]140 fault_if_from_uspace(istate, "Stack fault.");
[62baed17]141 panic_badtrap(istate, n, "Stack fault.");
[6de2480e]142}
143
[214ec25c]144static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
[3b05862f]145{
[7f1c620]146 uint32_t mxcsr;
[da1bafb]147 asm volatile (
[add04f7]148 "stmxcsr %[mxcsr]\n"
149 : [mxcsr] "=m" (mxcsr)
[3b05862f]150 );
[da1bafb]151
[7e752b2]152 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
153 mxcsr);
154 panic_badtrap(istate, n, "SIMD FP exception");
[3b05862f]155}
156
[214ec25c]157static void nm_fault(unsigned int n __attribute__((unused)),
[da1bafb]158 istate_t *istate __attribute__((unused)))
[6a27d63]159{
[da1bafb]160#ifdef CONFIG_FPU_LAZY
[b49f4ae]161 scheduler_fpu_lazy_request();
162#else
[f651e80]163 fault_if_from_uspace(istate, "FPU fault.");
[62baed17]164 panic_badtrap(istate, n, "FPU fault.");
[b49f4ae]165#endif
[6a27d63]166}
167
[cea12e9]168#ifdef CONFIG_SMP
[214ec25c]169static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
[da1bafb]170 istate_t *istate __attribute__((unused)))
[f761f1eb]171{
[cea12e9]172 trap_virtual_eoi();
173 tlb_shootdown_ipi_recv();
[f761f1eb]174}
[2ee1ccc]175
176static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
177{
178 trap_virtual_eoi();
179 smp_call_ipi_recv();
180}
[cea12e9]181#endif
[f761f1eb]182
[cea12e9]183/** Handler of IRQ exceptions */
[214ec25c]184static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
[169587a]185{
[63e27ef]186 assert(n >= IVT_IRQBASE);
[cea12e9]187
[214ec25c]188 unsigned int inum = n - IVT_IRQBASE;
[7bcfbbc]189 bool ack = false;
[63e27ef]190 assert(inum < IRQ_COUNT);
191 assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
[7bcfbbc]192
[cea12e9]193 irq_t *irq = irq_dispatch_and_lock(inum);
194 if (irq) {
195 /*
196 * The IRQ handler was found.
197 */
[da1bafb]198
[7bcfbbc]199 if (irq->preack) {
200 /* Send EOI before processing the interrupt */
201 trap_virtual_eoi();
202 ack = true;
203 }
[6cd9aa6]204 irq->handler(irq);
[da1bafb]205 irq_spinlock_unlock(&irq->lock, false);
[cea12e9]206 } else {
207 /*
208 * Spurious interrupt.
209 */
210#ifdef CONFIG_DEBUG
[214ec25c]211 printf("cpu%u: spurious interrupt (inum=%u)\n", CPU->id, inum);
[cea12e9]212#endif
213 }
[7bcfbbc]214
215 if (!ack)
216 trap_virtual_eoi();
[cea12e9]217}
218
219void interrupt_init(void)
220{
[b3b7e14a]221 unsigned int i;
[cea12e9]222
223 for (i = 0; i < IVT_ITEMS; i++)
[b3b7e14a]224 exc_register(i, "null", false, (iroutine_t) null_interrupt);
[cea12e9]225
226 for (i = 0; i < IRQ_COUNT; i++) {
227 if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
[b3b7e14a]228 exc_register(IVT_IRQBASE + i, "irq", true,
229 (iroutine_t) irq_interrupt);
[cea12e9]230 }
231
[4b0206c]232 exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
233 exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
234 exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
235 exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
236 exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception);
[cea12e9]237
238#ifdef CONFIG_SMP
[b3b7e14a]239 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
240 (iroutine_t) tlb_shootdown_ipi);
[2ee1ccc]241 exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
242 (iroutine_t) arch_smp_call_ipi_recv);
[cea12e9]243#endif
[169587a]244}
245
[7f1c620]246void trap_virtual_enable_irqs(uint16_t irqmask)
[f761f1eb]247{
248 if (enable_irqs_function)
249 enable_irqs_function(irqmask);
250 else
[f651e80]251 panic("No enable_irqs_function.");
[f761f1eb]252}
253
[7f1c620]254void trap_virtual_disable_irqs(uint16_t irqmask)
[f761f1eb]255{
256 if (disable_irqs_function)
257 disable_irqs_function(irqmask);
258 else
[f651e80]259 panic("No disable_irqs_function.");
[f761f1eb]260}
261
[3222efd]262/** @}
[b45c443]263 */
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