[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_ia32_interrupt
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[f761f1eb] | 35 | #include <arch/interrupt.h>
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[63e27ef] | 36 | #include <assert.h>
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[204674e] | 37 | #include <syscall/syscall.h>
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[bab75df6] | 38 | #include <stdio.h>
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[02a99d2] | 39 | #include <debug.h>
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[f761f1eb] | 40 | #include <panic.h>
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[80d31883] | 41 | #include <arch/drivers/i8259.h>
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[b2e121a] | 42 | #include <halt.h>
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[f761f1eb] | 43 | #include <cpu.h>
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| 44 | #include <arch/asm.h>
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[169587a] | 45 | #include <mm/tlb.h>
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[20d50a1] | 46 | #include <mm/as.h>
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[cb4b61d] | 47 | #include <arch.h>
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[1084a784] | 48 | #include <proc/thread.h>
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[2382d09] | 49 | #include <proc/task.h>
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| 50 | #include <synch/spinlock.h>
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| 51 | #include <arch/ddi/ddi.h>
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[5626277] | 52 | #include <ipc/sysipc.h>
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| 53 | #include <interrupt.h>
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[cea12e9] | 54 | #include <ddi/irq.h>
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[e2b762ec] | 55 | #include <symtab.h>
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[203deeb8] | 56 | #include <stacktrace.h>
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[2ee1ccc] | 57 | #include <smp/smp_call.h>
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[1066041] | 58 | #include <proc/task.h>
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[e2b762ec] | 59 |
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[f761f1eb] | 60 | /*
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| 61 | * Interrupt and exception dispatching.
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| 62 | */
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| 63 |
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[1433ecda] | 64 | void (*disable_irqs_function)(uint16_t irqmask) = NULL;
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| 65 | void (*enable_irqs_function)(uint16_t irqmask) = NULL;
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| 66 | void (*eoi_function)(void) = NULL;
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[acc7ce4] | 67 | const char *irqs_info = NULL;
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[f761f1eb] | 68 |
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[22a28a69] | 69 | void istate_decode(istate_t *istate)
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[97b64c9] | 70 | {
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[f36787d7] | 71 | printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
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| 72 | "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
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| 73 | istate->cs, istate->eip, istate->eflags, istate->error_word);
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[a35b458] | 74 |
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[f36787d7] | 75 | printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
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| 76 | "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
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[0d1e976] | 77 | istate->ds, istate->es, istate->fs, istate->gs);
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[a35b458] | 78 |
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[c9eb31c2] | 79 | if (istate_from_uspace(istate))
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[f36787d7] | 80 | printf("ss =%0#10" PRIx32 "\n", istate->ss);
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[a35b458] | 81 |
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[f36787d7] | 82 | printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
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| 83 | "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
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[0d1e976] | 84 | istate->eax, istate->ebx, istate->ecx, istate->edx);
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[a35b458] | 85 |
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[f36787d7] | 86 | printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
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[fd57745c] | 87 | "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
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[f36787d7] | 88 | istate->esi, istate->edi, istate->ebp,
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| 89 | istate_from_uspace(istate) ? istate->esp :
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[35ebd42] | 90 | (uint32_t) &istate->esp);
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[97b64c9] | 91 | }
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[ab08b42] | 92 |
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[cea12e9] | 93 | static void trap_virtual_eoi(void)
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| 94 | {
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| 95 | if (eoi_function)
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| 96 | eoi_function();
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| 97 | else
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[f651e80] | 98 | panic("No eoi_function.");
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[cea12e9] | 99 |
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| 100 | }
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| 101 |
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[214ec25c] | 102 | static void null_interrupt(unsigned int n, istate_t *istate)
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[f761f1eb] | 103 | {
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[214ec25c] | 104 | fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
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[62baed17] | 105 | panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
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[f761f1eb] | 106 | }
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| 107 |
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[214ec25c] | 108 | static void de_fault(unsigned int n, istate_t *istate)
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[4491338] | 109 | {
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| 110 | fault_if_from_uspace(istate, "Divide error.");
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[62baed17] | 111 | panic_badtrap(istate, n, "Divide error.");
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[4491338] | 112 | }
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| 113 |
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[ae89656] | 114 | static void db_exception(unsigned int n, istate_t *istate)
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| 115 | {
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| 116 | /*
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| 117 | * We need to provide at least an empty handler that does not panic
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| 118 | * if the exception appears to come from the kernel because the
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| 119 | * userspace can inject a kernel-level #DB after e.g. the SYSENTER
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| 120 | * instruction if the EFLAGS.TF is set.
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| 121 | */
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| 122 | }
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| 123 |
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[2382d09] | 124 | /** General Protection Fault. */
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[214ec25c] | 125 | static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
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[f761f1eb] | 126 | {
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[2382d09] | 127 | if (TASK) {
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[da1bafb] | 128 | irq_spinlock_lock(&TASK->lock, false);
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| 129 | size_t ver = TASK->arch.iomapver;
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| 130 | irq_spinlock_unlock(&TASK->lock, false);
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[a35b458] | 131 |
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[2382d09] | 132 | if (CPU->arch.iomapver_copy != ver) {
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| 133 | /*
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| 134 | * This fault can be caused by an early access
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| 135 | * to I/O port because of an out-dated
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| 136 | * I/O Permission bitmap installed on CPU.
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| 137 | * Install the fresh copy and restart
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| 138 | * the instruction.
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| 139 | */
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| 140 | io_perm_bitmap_install();
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| 141 | return;
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| 142 | }
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[f651e80] | 143 | fault_if_from_uspace(istate, "General protection fault.");
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[2382d09] | 144 | }
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[62baed17] | 145 | panic_badtrap(istate, n, "General protection fault.");
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[f761f1eb] | 146 | }
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| 147 |
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[214ec25c] | 148 | static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
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[6de2480e] | 149 | {
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[f651e80] | 150 | fault_if_from_uspace(istate, "Stack fault.");
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[62baed17] | 151 | panic_badtrap(istate, n, "Stack fault.");
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[6de2480e] | 152 | }
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| 153 |
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[214ec25c] | 154 | static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
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[3b05862f] | 155 | {
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[7f1c620] | 156 | uint32_t mxcsr;
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[da1bafb] | 157 | asm volatile (
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[1433ecda] | 158 | "stmxcsr %[mxcsr]\n"
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| 159 | : [mxcsr] "=m" (mxcsr)
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[3b05862f] | 160 | );
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[a35b458] | 161 |
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[7e752b2] | 162 | fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
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| 163 | mxcsr);
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| 164 | panic_badtrap(istate, n, "SIMD FP exception");
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[3b05862f] | 165 | }
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| 166 |
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[214ec25c] | 167 | static void nm_fault(unsigned int n __attribute__((unused)),
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[da1bafb] | 168 | istate_t *istate __attribute__((unused)))
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[6a27d63] | 169 | {
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[da1bafb] | 170 | #ifdef CONFIG_FPU_LAZY
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[b49f4ae] | 171 | scheduler_fpu_lazy_request();
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| 172 | #else
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[f651e80] | 173 | fault_if_from_uspace(istate, "FPU fault.");
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[62baed17] | 174 | panic_badtrap(istate, n, "FPU fault.");
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[b49f4ae] | 175 | #endif
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[6a27d63] | 176 | }
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| 177 |
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[cea12e9] | 178 | #ifdef CONFIG_SMP
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[214ec25c] | 179 | static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
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[da1bafb] | 180 | istate_t *istate __attribute__((unused)))
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[f761f1eb] | 181 | {
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[cea12e9] | 182 | trap_virtual_eoi();
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| 183 | tlb_shootdown_ipi_recv();
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[f761f1eb] | 184 | }
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[2ee1ccc] | 185 |
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| 186 | static void arch_smp_call_ipi_recv(unsigned int n, istate_t *istate)
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| 187 | {
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| 188 | trap_virtual_eoi();
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| 189 | smp_call_ipi_recv();
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| 190 | }
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[cea12e9] | 191 | #endif
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[f761f1eb] | 192 |
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[cea12e9] | 193 | /** Handler of IRQ exceptions */
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[214ec25c] | 194 | static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
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[169587a] | 195 | {
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[63e27ef] | 196 | assert(n >= IVT_IRQBASE);
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[a35b458] | 197 |
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[214ec25c] | 198 | unsigned int inum = n - IVT_IRQBASE;
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[7bcfbbc] | 199 | bool ack = false;
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[63e27ef] | 200 | assert(inum < IRQ_COUNT);
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| 201 | assert((inum != IRQ_PIC_SPUR) && (inum != IRQ_PIC1));
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[a35b458] | 202 |
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[cea12e9] | 203 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 204 | if (irq) {
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| 205 | /*
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| 206 | * The IRQ handler was found.
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| 207 | */
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[a35b458] | 208 |
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[7bcfbbc] | 209 | if (irq->preack) {
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| 210 | /* Send EOI before processing the interrupt */
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| 211 | trap_virtual_eoi();
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| 212 | ack = true;
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| 213 | }
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[6cd9aa6] | 214 | irq->handler(irq);
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[da1bafb] | 215 | irq_spinlock_unlock(&irq->lock, false);
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[cea12e9] | 216 | } else {
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| 217 | /*
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| 218 | * Spurious interrupt.
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| 219 | */
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| 220 | #ifdef CONFIG_DEBUG
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[214ec25c] | 221 | printf("cpu%u: spurious interrupt (inum=%u)\n", CPU->id, inum);
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[cea12e9] | 222 | #endif
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| 223 | }
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[a35b458] | 224 |
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[7bcfbbc] | 225 | if (!ack)
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| 226 | trap_virtual_eoi();
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[cea12e9] | 227 | }
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| 228 |
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| 229 | void interrupt_init(void)
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| 230 | {
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[b3b7e14a] | 231 | unsigned int i;
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[a35b458] | 232 |
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[cea12e9] | 233 | for (i = 0; i < IVT_ITEMS; i++)
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[b3b7e14a] | 234 | exc_register(i, "null", false, (iroutine_t) null_interrupt);
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[a35b458] | 235 |
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[cea12e9] | 236 | for (i = 0; i < IRQ_COUNT; i++) {
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| 237 | if ((i != IRQ_PIC_SPUR) && (i != IRQ_PIC1))
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[b3b7e14a] | 238 | exc_register(IVT_IRQBASE + i, "irq", true,
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| 239 | (iroutine_t) irq_interrupt);
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[cea12e9] | 240 | }
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[a35b458] | 241 |
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[4b0206c] | 242 | exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
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[ae89656] | 243 | exc_register(VECTOR_DB, "db_exc", true, (iroutine_t) db_exception);
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[4b0206c] | 244 | exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
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| 245 | exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
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| 246 | exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
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| 247 | exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception);
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[a35b458] | 248 |
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[cea12e9] | 249 | #ifdef CONFIG_SMP
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[b3b7e14a] | 250 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
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| 251 | (iroutine_t) tlb_shootdown_ipi);
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[2ee1ccc] | 252 | exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
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| 253 | (iroutine_t) arch_smp_call_ipi_recv);
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[cea12e9] | 254 | #endif
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[169587a] | 255 | }
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| 256 |
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[7f1c620] | 257 | void trap_virtual_enable_irqs(uint16_t irqmask)
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[f761f1eb] | 258 | {
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| 259 | if (enable_irqs_function)
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| 260 | enable_irqs_function(irqmask);
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| 261 | else
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[f651e80] | 262 | panic("No enable_irqs_function.");
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[f761f1eb] | 263 | }
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| 264 |
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[7f1c620] | 265 | void trap_virtual_disable_irqs(uint16_t irqmask)
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[f761f1eb] | 266 | {
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| 267 | if (disable_irqs_function)
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| 268 | disable_irqs_function(irqmask);
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| 269 | else
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[f651e80] | 270 | panic("No disable_irqs_function.");
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[f761f1eb] | 271 | }
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| 272 |
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[3222efd] | 273 | /** @}
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[b45c443] | 274 | */
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