source: mainline/kernel/arch/ia32/src/interrupt.c@ 3daba42e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3daba42e was fd67c9f, checked in by Jakub Jermar <jakub@…>, 7 years ago

Handle PIC spurious IRQs with care

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File size: 7.8 KB
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[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_ia32_interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/interrupt.h>
[63e27ef]36#include <assert.h>
[204674e]37#include <syscall/syscall.h>
[bab75df6]38#include <stdio.h>
[02a99d2]39#include <debug.h>
[f761f1eb]40#include <panic.h>
[87a5796]41#include <genarch/drivers/i8259/i8259.h>
[b2e121a]42#include <halt.h>
[f761f1eb]43#include <cpu.h>
44#include <arch/asm.h>
[169587a]45#include <mm/tlb.h>
[20d50a1]46#include <mm/as.h>
[cb4b61d]47#include <arch.h>
[1084a784]48#include <proc/thread.h>
[2382d09]49#include <proc/task.h>
50#include <synch/spinlock.h>
51#include <arch/ddi/ddi.h>
[5626277]52#include <ipc/sysipc.h>
53#include <interrupt.h>
[cea12e9]54#include <ddi/irq.h>
[e2b762ec]55#include <symtab.h>
[203deeb8]56#include <stacktrace.h>
[1066041]57#include <proc/task.h>
[e2b762ec]58
[f761f1eb]59/*
60 * Interrupt and exception dispatching.
61 */
62
[1433ecda]63void (*disable_irqs_function)(uint16_t irqmask) = NULL;
64void (*enable_irqs_function)(uint16_t irqmask) = NULL;
[ef56a43]65void (*eoi_function)(unsigned int) = NULL;
[acc7ce4]66const char *irqs_info = NULL;
[f761f1eb]67
[22a28a69]68void istate_decode(istate_t *istate)
[97b64c9]69{
[f36787d7]70 printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
71 "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
72 istate->cs, istate->eip, istate->eflags, istate->error_word);
[a35b458]73
[f36787d7]74 printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
75 "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
[0d1e976]76 istate->ds, istate->es, istate->fs, istate->gs);
[a35b458]77
[c9eb31c2]78 if (istate_from_uspace(istate))
[f36787d7]79 printf("ss =%0#10" PRIx32 "\n", istate->ss);
[a35b458]80
[f36787d7]81 printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
82 "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
[0d1e976]83 istate->eax, istate->ebx, istate->ecx, istate->edx);
[a35b458]84
[f36787d7]85 printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
[fd57745c]86 "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
[f36787d7]87 istate->esi, istate->edi, istate->ebp,
88 istate_from_uspace(istate) ? istate->esp :
[35ebd42]89 (uint32_t) &istate->esp);
[97b64c9]90}
[ab08b42]91
[ef56a43]92static void trap_virtual_eoi(unsigned int inum)
[cea12e9]93{
94 if (eoi_function)
[ef56a43]95 eoi_function(inum);
[cea12e9]96 else
[f651e80]97 panic("No eoi_function.");
[cea12e9]98
99}
100
[214ec25c]101static void null_interrupt(unsigned int n, istate_t *istate)
[f761f1eb]102{
[214ec25c]103 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
[62baed17]104 panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
[f761f1eb]105}
106
[214ec25c]107static void de_fault(unsigned int n, istate_t *istate)
[4491338]108{
109 fault_if_from_uspace(istate, "Divide error.");
[62baed17]110 panic_badtrap(istate, n, "Divide error.");
[4491338]111}
112
[ae89656]113static void db_exception(unsigned int n, istate_t *istate)
114{
115 /*
116 * We need to provide at least an empty handler that does not panic
117 * if the exception appears to come from the kernel because the
118 * userspace can inject a kernel-level #DB after e.g. the SYSENTER
119 * instruction if the EFLAGS.TF is set.
120 */
121}
122
[2382d09]123/** General Protection Fault. */
[214ec25c]124static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[f761f1eb]125{
[2382d09]126 if (TASK) {
[da1bafb]127 irq_spinlock_lock(&TASK->lock, false);
128 size_t ver = TASK->arch.iomapver;
129 irq_spinlock_unlock(&TASK->lock, false);
[a35b458]130
[2382d09]131 if (CPU->arch.iomapver_copy != ver) {
132 /*
133 * This fault can be caused by an early access
134 * to I/O port because of an out-dated
135 * I/O Permission bitmap installed on CPU.
136 * Install the fresh copy and restart
137 * the instruction.
138 */
139 io_perm_bitmap_install();
140 return;
141 }
[f651e80]142 fault_if_from_uspace(istate, "General protection fault.");
[2382d09]143 }
[62baed17]144 panic_badtrap(istate, n, "General protection fault.");
[f761f1eb]145}
146
[214ec25c]147static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[6de2480e]148{
[f651e80]149 fault_if_from_uspace(istate, "Stack fault.");
[62baed17]150 panic_badtrap(istate, n, "Stack fault.");
[6de2480e]151}
152
[214ec25c]153static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
[3b05862f]154{
[7f1c620]155 uint32_t mxcsr;
[da1bafb]156 asm volatile (
[1433ecda]157 "stmxcsr %[mxcsr]\n"
158 : [mxcsr] "=m" (mxcsr)
[3b05862f]159 );
[a35b458]160
[7e752b2]161 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
162 mxcsr);
163 panic_badtrap(istate, n, "SIMD FP exception");
[3b05862f]164}
165
[214ec25c]166static void nm_fault(unsigned int n __attribute__((unused)),
[da1bafb]167 istate_t *istate __attribute__((unused)))
[6a27d63]168{
[da1bafb]169#ifdef CONFIG_FPU_LAZY
[b49f4ae]170 scheduler_fpu_lazy_request();
171#else
[f651e80]172 fault_if_from_uspace(istate, "FPU fault.");
[62baed17]173 panic_badtrap(istate, n, "FPU fault.");
[b49f4ae]174#endif
[6a27d63]175}
176
[cea12e9]177#ifdef CONFIG_SMP
[214ec25c]178static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
[da1bafb]179 istate_t *istate __attribute__((unused)))
[f761f1eb]180{
[ef56a43]181 trap_virtual_eoi(0);
[cea12e9]182 tlb_shootdown_ipi_recv();
[f761f1eb]183}
[cea12e9]184#endif
[f761f1eb]185
[cea12e9]186/** Handler of IRQ exceptions */
[214ec25c]187static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
[169587a]188{
[63e27ef]189 assert(n >= IVT_IRQBASE);
[a35b458]190
[214ec25c]191 unsigned int inum = n - IVT_IRQBASE;
[7bcfbbc]192 bool ack = false;
[63e27ef]193 assert(inum < IRQ_COUNT);
[f6cf76f]194 assert(inum != IRQ_PIC1);
[a35b458]195
[cea12e9]196 irq_t *irq = irq_dispatch_and_lock(inum);
197 if (irq) {
198 /*
199 * The IRQ handler was found.
200 */
[a35b458]201
[7bcfbbc]202 if (irq->preack) {
203 /* Send EOI before processing the interrupt */
[ef56a43]204 trap_virtual_eoi(inum);
[7bcfbbc]205 ack = true;
206 }
[6cd9aa6]207 irq->handler(irq);
[da1bafb]208 irq_spinlock_unlock(&irq->lock, false);
[cea12e9]209 } else {
210#ifdef CONFIG_DEBUG
[fd67c9f]211 log(LF_ARCH, LVL_DEBUG, "cpu%u: unhandled IRQ %u", CPU->id,
212 inum);
[cea12e9]213#endif
214 }
[a35b458]215
[7bcfbbc]216 if (!ack)
[ef56a43]217 trap_virtual_eoi(inum);
[cea12e9]218}
219
[f6cf76f]220static void pic_spurious(unsigned int n, istate_t *istate)
221{
[fd67c9f]222 unsigned int inum = n - IVT_IRQBASE;
223 if (!pic_is_spurious(inum)) {
224 /* This is actually not a spurious IRQ, so proceed as usual. */
225 irq_interrupt(n, istate);
226 return;
227 }
228 pic_handle_spurious(n);
[f6cf76f]229#ifdef CONFIG_DEBUG
[fd67c9f]230 log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt %u", CPU->id,
231 inum);
[f6cf76f]232#endif
233}
234
[cea12e9]235void interrupt_init(void)
236{
[b3b7e14a]237 unsigned int i;
[a35b458]238
[cea12e9]239 for (i = 0; i < IVT_ITEMS; i++)
[b3b7e14a]240 exc_register(i, "null", false, (iroutine_t) null_interrupt);
[a35b458]241
[cea12e9]242 for (i = 0; i < IRQ_COUNT; i++) {
[f6cf76f]243 if ((i != IRQ_PIC0_SPUR) && (i != IRQ_PIC1_SPUR) &&
244 (i != IRQ_PIC1))
[b3b7e14a]245 exc_register(IVT_IRQBASE + i, "irq", true,
246 (iroutine_t) irq_interrupt);
[cea12e9]247 }
[a35b458]248
[4b0206c]249 exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
[ae89656]250 exc_register(VECTOR_DB, "db_exc", true, (iroutine_t) db_exception);
[4b0206c]251 exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
252 exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
253 exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
254 exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception);
[f6cf76f]255 exc_register(VECTOR_PIC0_SPUR, "pic0_spurious", true,
256 (iroutine_t) pic_spurious);
257 exc_register(VECTOR_PIC1_SPUR, "pic1_spurious", true,
258 (iroutine_t) pic_spurious);
[a35b458]259
[cea12e9]260#ifdef CONFIG_SMP
[b3b7e14a]261 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
262 (iroutine_t) tlb_shootdown_ipi);
[cea12e9]263#endif
[169587a]264}
265
[7f1c620]266void trap_virtual_enable_irqs(uint16_t irqmask)
[f761f1eb]267{
268 if (enable_irqs_function)
269 enable_irqs_function(irqmask);
270 else
[f651e80]271 panic("No enable_irqs_function.");
[f761f1eb]272}
273
[7f1c620]274void trap_virtual_disable_irqs(uint16_t irqmask)
[f761f1eb]275{
276 if (disable_irqs_function)
277 disable_irqs_function(irqmask);
278 else
[f651e80]279 panic("No disable_irqs_function.");
[f761f1eb]280}
281
[3222efd]282/** @}
[b45c443]283 */
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