[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[c5429fe] | 29 | /** @addtogroup kernel_ia32_interrupt
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[f761f1eb] | 35 | #include <arch/interrupt.h>
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[63e27ef] | 36 | #include <assert.h>
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[204674e] | 37 | #include <syscall/syscall.h>
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[bab75df6] | 38 | #include <stdio.h>
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[02a99d2] | 39 | #include <debug.h>
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[f761f1eb] | 40 | #include <panic.h>
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[87a5796] | 41 | #include <genarch/drivers/i8259/i8259.h>
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[2a103b5] | 42 | #include <genarch/pic/pic_ops.h>
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[b2e121a] | 43 | #include <halt.h>
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[f761f1eb] | 44 | #include <cpu.h>
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| 45 | #include <arch/asm.h>
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[169587a] | 46 | #include <mm/tlb.h>
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[20d50a1] | 47 | #include <mm/as.h>
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[cb4b61d] | 48 | #include <arch.h>
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[1084a784] | 49 | #include <proc/thread.h>
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[2382d09] | 50 | #include <proc/task.h>
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| 51 | #include <synch/spinlock.h>
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| 52 | #include <arch/ddi/ddi.h>
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[5626277] | 53 | #include <ipc/sysipc.h>
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| 54 | #include <interrupt.h>
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[cea12e9] | 55 | #include <ddi/irq.h>
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[e2b762ec] | 56 | #include <symtab.h>
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[203deeb8] | 57 | #include <stacktrace.h>
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[1066041] | 58 | #include <proc/task.h>
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[e2b762ec] | 59 |
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[f761f1eb] | 60 | /*
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| 61 | * Interrupt and exception dispatching.
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| 62 | */
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| 63 |
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[2a103b5] | 64 | pic_ops_t *pic_ops = NULL;
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[f761f1eb] | 65 |
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[22a28a69] | 66 | void istate_decode(istate_t *istate)
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[97b64c9] | 67 | {
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[f36787d7] | 68 | printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
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| 69 | "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
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| 70 | istate->cs, istate->eip, istate->eflags, istate->error_word);
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[a35b458] | 71 |
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[f36787d7] | 72 | printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
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| 73 | "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
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[0d1e976] | 74 | istate->ds, istate->es, istate->fs, istate->gs);
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[a35b458] | 75 |
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[c9eb31c2] | 76 | if (istate_from_uspace(istate))
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[f36787d7] | 77 | printf("ss =%0#10" PRIx32 "\n", istate->ss);
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[a35b458] | 78 |
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[f36787d7] | 79 | printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
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| 80 | "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
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[0d1e976] | 81 | istate->eax, istate->ebx, istate->ecx, istate->edx);
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[a35b458] | 82 |
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[f36787d7] | 83 | printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
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[fd57745c] | 84 | "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
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[f36787d7] | 85 | istate->esi, istate->edi, istate->ebp,
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| 86 | istate_from_uspace(istate) ? istate->esp :
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[35ebd42] | 87 | (uint32_t) &istate->esp);
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[97b64c9] | 88 | }
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[ab08b42] | 89 |
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[214ec25c] | 90 | static void null_interrupt(unsigned int n, istate_t *istate)
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[f761f1eb] | 91 | {
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[214ec25c] | 92 | fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
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[62baed17] | 93 | panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
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[f761f1eb] | 94 | }
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| 95 |
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[214ec25c] | 96 | static void de_fault(unsigned int n, istate_t *istate)
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[4491338] | 97 | {
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| 98 | fault_if_from_uspace(istate, "Divide error.");
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[62baed17] | 99 | panic_badtrap(istate, n, "Divide error.");
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[4491338] | 100 | }
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| 101 |
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[ae89656] | 102 | static void db_exception(unsigned int n, istate_t *istate)
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| 103 | {
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| 104 | /*
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| 105 | * We need to provide at least an empty handler that does not panic
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| 106 | * if the exception appears to come from the kernel because the
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| 107 | * userspace can inject a kernel-level #DB after e.g. the SYSENTER
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| 108 | * instruction if the EFLAGS.TF is set.
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| 109 | */
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| 110 | }
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| 111 |
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[2382d09] | 112 | /** General Protection Fault. */
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[214ec25c] | 113 | static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
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[f761f1eb] | 114 | {
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[2382d09] | 115 | if (TASK) {
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[da1bafb] | 116 | irq_spinlock_lock(&TASK->lock, false);
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| 117 | size_t ver = TASK->arch.iomapver;
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| 118 | irq_spinlock_unlock(&TASK->lock, false);
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[a35b458] | 119 |
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[2382d09] | 120 | if (CPU->arch.iomapver_copy != ver) {
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| 121 | /*
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| 122 | * This fault can be caused by an early access
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| 123 | * to I/O port because of an out-dated
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| 124 | * I/O Permission bitmap installed on CPU.
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| 125 | * Install the fresh copy and restart
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| 126 | * the instruction.
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| 127 | */
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| 128 | io_perm_bitmap_install();
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| 129 | return;
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| 130 | }
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[f651e80] | 131 | fault_if_from_uspace(istate, "General protection fault.");
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[2382d09] | 132 | }
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[62baed17] | 133 | panic_badtrap(istate, n, "General protection fault.");
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[f761f1eb] | 134 | }
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| 135 |
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[214ec25c] | 136 | static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
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[6de2480e] | 137 | {
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[f651e80] | 138 | fault_if_from_uspace(istate, "Stack fault.");
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[62baed17] | 139 | panic_badtrap(istate, n, "Stack fault.");
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[6de2480e] | 140 | }
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| 141 |
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[214ec25c] | 142 | static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
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[3b05862f] | 143 | {
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[7f1c620] | 144 | uint32_t mxcsr;
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[da1bafb] | 145 | asm volatile (
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[1433ecda] | 146 | "stmxcsr %[mxcsr]\n"
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| 147 | : [mxcsr] "=m" (mxcsr)
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[3b05862f] | 148 | );
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[a35b458] | 149 |
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[7e752b2] | 150 | fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
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| 151 | mxcsr);
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| 152 | panic_badtrap(istate, n, "SIMD FP exception");
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[3b05862f] | 153 | }
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| 154 |
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[214ec25c] | 155 | static void nm_fault(unsigned int n __attribute__((unused)),
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[da1bafb] | 156 | istate_t *istate __attribute__((unused)))
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[6a27d63] | 157 | {
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[da1bafb] | 158 | #ifdef CONFIG_FPU_LAZY
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[b49f4ae] | 159 | scheduler_fpu_lazy_request();
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| 160 | #else
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[f651e80] | 161 | fault_if_from_uspace(istate, "FPU fault.");
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[62baed17] | 162 | panic_badtrap(istate, n, "FPU fault.");
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[b49f4ae] | 163 | #endif
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[6a27d63] | 164 | }
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| 165 |
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[cea12e9] | 166 | #ifdef CONFIG_SMP
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[214ec25c] | 167 | static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
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[da1bafb] | 168 | istate_t *istate __attribute__((unused)))
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[f761f1eb] | 169 | {
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[2a103b5] | 170 | pic_ops->eoi(0);
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[cea12e9] | 171 | tlb_shootdown_ipi_recv();
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[f761f1eb] | 172 | }
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[cea12e9] | 173 | #endif
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[f761f1eb] | 174 |
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[cea12e9] | 175 | /** Handler of IRQ exceptions */
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[214ec25c] | 176 | static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
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[169587a] | 177 | {
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[63e27ef] | 178 | assert(n >= IVT_IRQBASE);
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[a35b458] | 179 |
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[214ec25c] | 180 | unsigned int inum = n - IVT_IRQBASE;
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[7bcfbbc] | 181 | bool ack = false;
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[63e27ef] | 182 | assert(inum < IRQ_COUNT);
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[f6cf76f] | 183 | assert(inum != IRQ_PIC1);
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[a35b458] | 184 |
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[cea12e9] | 185 | irq_t *irq = irq_dispatch_and_lock(inum);
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| 186 | if (irq) {
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| 187 | /*
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| 188 | * The IRQ handler was found.
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| 189 | */
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[a35b458] | 190 |
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[7bcfbbc] | 191 | if (irq->preack) {
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| 192 | /* Send EOI before processing the interrupt */
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[2a103b5] | 193 | pic_ops->eoi(inum);
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[7bcfbbc] | 194 | ack = true;
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| 195 | }
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[6cd9aa6] | 196 | irq->handler(irq);
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[da1bafb] | 197 | irq_spinlock_unlock(&irq->lock, false);
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[cea12e9] | 198 | } else {
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| 199 | #ifdef CONFIG_DEBUG
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[fd67c9f] | 200 | log(LF_ARCH, LVL_DEBUG, "cpu%u: unhandled IRQ %u", CPU->id,
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| 201 | inum);
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[cea12e9] | 202 | #endif
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| 203 | }
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[a35b458] | 204 |
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[7bcfbbc] | 205 | if (!ack)
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[2a103b5] | 206 | pic_ops->eoi(inum);
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[cea12e9] | 207 | }
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| 208 |
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[f6cf76f] | 209 | static void pic_spurious(unsigned int n, istate_t *istate)
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| 210 | {
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[fd67c9f] | 211 | unsigned int inum = n - IVT_IRQBASE;
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[2a103b5] | 212 | if (!pic_ops->is_spurious(inum)) {
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[fd67c9f] | 213 | /* This is actually not a spurious IRQ, so proceed as usual. */
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| 214 | irq_interrupt(n, istate);
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| 215 | return;
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| 216 | }
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[2a103b5] | 217 | pic_ops->handle_spurious(n);
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[f6cf76f] | 218 | #ifdef CONFIG_DEBUG
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[fd67c9f] | 219 | log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt %u", CPU->id,
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| 220 | inum);
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[f6cf76f] | 221 | #endif
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| 222 | }
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| 223 |
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[cea12e9] | 224 | void interrupt_init(void)
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| 225 | {
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[b3b7e14a] | 226 | unsigned int i;
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[a35b458] | 227 |
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[cea12e9] | 228 | for (i = 0; i < IVT_ITEMS; i++)
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[b3b7e14a] | 229 | exc_register(i, "null", false, (iroutine_t) null_interrupt);
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[a35b458] | 230 |
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[cea12e9] | 231 | for (i = 0; i < IRQ_COUNT; i++) {
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[f6cf76f] | 232 | if ((i != IRQ_PIC0_SPUR) && (i != IRQ_PIC1_SPUR) &&
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| 233 | (i != IRQ_PIC1))
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[b3b7e14a] | 234 | exc_register(IVT_IRQBASE + i, "irq", true,
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| 235 | (iroutine_t) irq_interrupt);
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[cea12e9] | 236 | }
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[a35b458] | 237 |
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[4b0206c] | 238 | exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
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[ae89656] | 239 | exc_register(VECTOR_DB, "db_exc", true, (iroutine_t) db_exception);
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[4b0206c] | 240 | exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
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| 241 | exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
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| 242 | exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
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| 243 | exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception);
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[f6cf76f] | 244 | exc_register(VECTOR_PIC0_SPUR, "pic0_spurious", true,
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| 245 | (iroutine_t) pic_spurious);
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| 246 | exc_register(VECTOR_PIC1_SPUR, "pic1_spurious", true,
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| 247 | (iroutine_t) pic_spurious);
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[a35b458] | 248 |
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[cea12e9] | 249 | #ifdef CONFIG_SMP
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[b3b7e14a] | 250 | exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
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| 251 | (iroutine_t) tlb_shootdown_ipi);
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[cea12e9] | 252 | #endif
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[169587a] | 253 | }
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| 254 |
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[3222efd] | 255 | /** @}
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[b45c443] | 256 | */
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