source: mainline/kernel/arch/ia32/src/interrupt.c

Last change on this file was 2a103b5, checked in by Jakub Jermar <jakub@…>, 6 years ago

Introduce PIC operations indirection mechanism

Some architectures switch from one interrupt controller implementation
to another during runtime. By providing a cleaner indirection mechanism,
it is possible e.g. for the ia32 IRQ 7 handler to distinguish i8259
spurious interrupts from actual IRQ 7 device interrupts, even when the
i8259 interrupt controller is no longer active.

  • Property mode set to 100644
File size: 7.3 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[c5429fe]29/** @addtogroup kernel_ia32_interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/interrupt.h>
[63e27ef]36#include <assert.h>
[204674e]37#include <syscall/syscall.h>
[bab75df6]38#include <stdio.h>
[02a99d2]39#include <debug.h>
[f761f1eb]40#include <panic.h>
[87a5796]41#include <genarch/drivers/i8259/i8259.h>
[2a103b5]42#include <genarch/pic/pic_ops.h>
[b2e121a]43#include <halt.h>
[f761f1eb]44#include <cpu.h>
45#include <arch/asm.h>
[169587a]46#include <mm/tlb.h>
[20d50a1]47#include <mm/as.h>
[cb4b61d]48#include <arch.h>
[1084a784]49#include <proc/thread.h>
[2382d09]50#include <proc/task.h>
51#include <synch/spinlock.h>
52#include <arch/ddi/ddi.h>
[5626277]53#include <ipc/sysipc.h>
54#include <interrupt.h>
[cea12e9]55#include <ddi/irq.h>
[e2b762ec]56#include <symtab.h>
[203deeb8]57#include <stacktrace.h>
[1066041]58#include <proc/task.h>
[e2b762ec]59
[f761f1eb]60/*
61 * Interrupt and exception dispatching.
62 */
63
[2a103b5]64pic_ops_t *pic_ops = NULL;
[f761f1eb]65
[22a28a69]66void istate_decode(istate_t *istate)
[97b64c9]67{
[f36787d7]68 printf("cs =%0#10" PRIx32 "\teip=%0#10" PRIx32 "\t"
69 "efl=%0#10" PRIx32 "\terr=%0#10" PRIx32 "\n",
70 istate->cs, istate->eip, istate->eflags, istate->error_word);
[a35b458]71
[f36787d7]72 printf("ds =%0#10" PRIx32 "\tes =%0#10" PRIx32 "\t"
73 "fs =%0#10" PRIx32 "\tgs =%0#10" PRIx32 "\n",
[0d1e976]74 istate->ds, istate->es, istate->fs, istate->gs);
[a35b458]75
[c9eb31c2]76 if (istate_from_uspace(istate))
[f36787d7]77 printf("ss =%0#10" PRIx32 "\n", istate->ss);
[a35b458]78
[f36787d7]79 printf("eax=%0#10" PRIx32 "\tebx=%0#10" PRIx32 "\t"
80 "ecx=%0#10" PRIx32 "\tedx=%0#10" PRIx32 "\n",
[0d1e976]81 istate->eax, istate->ebx, istate->ecx, istate->edx);
[a35b458]82
[f36787d7]83 printf("esi=%0#10" PRIx32 "\tedi=%0#10" PRIx32 "\t"
[fd57745c]84 "ebp=%0#10" PRIx32 "\tesp=%0#10" PRIx32 "\n",
[f36787d7]85 istate->esi, istate->edi, istate->ebp,
86 istate_from_uspace(istate) ? istate->esp :
[35ebd42]87 (uint32_t) &istate->esp);
[97b64c9]88}
[ab08b42]89
[214ec25c]90static void null_interrupt(unsigned int n, istate_t *istate)
[f761f1eb]91{
[214ec25c]92 fault_if_from_uspace(istate, "Unserviced interrupt: %u.", n);
[62baed17]93 panic_badtrap(istate, n, "Unserviced interrupt: %u.", n);
[f761f1eb]94}
95
[214ec25c]96static void de_fault(unsigned int n, istate_t *istate)
[4491338]97{
98 fault_if_from_uspace(istate, "Divide error.");
[62baed17]99 panic_badtrap(istate, n, "Divide error.");
[4491338]100}
101
[ae89656]102static void db_exception(unsigned int n, istate_t *istate)
103{
104 /*
105 * We need to provide at least an empty handler that does not panic
106 * if the exception appears to come from the kernel because the
107 * userspace can inject a kernel-level #DB after e.g. the SYSENTER
108 * instruction if the EFLAGS.TF is set.
109 */
110}
111
[2382d09]112/** General Protection Fault. */
[214ec25c]113static void gp_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[f761f1eb]114{
[2382d09]115 if (TASK) {
[da1bafb]116 irq_spinlock_lock(&TASK->lock, false);
117 size_t ver = TASK->arch.iomapver;
118 irq_spinlock_unlock(&TASK->lock, false);
[a35b458]119
[2382d09]120 if (CPU->arch.iomapver_copy != ver) {
121 /*
122 * This fault can be caused by an early access
123 * to I/O port because of an out-dated
124 * I/O Permission bitmap installed on CPU.
125 * Install the fresh copy and restart
126 * the instruction.
127 */
128 io_perm_bitmap_install();
129 return;
130 }
[f651e80]131 fault_if_from_uspace(istate, "General protection fault.");
[2382d09]132 }
[62baed17]133 panic_badtrap(istate, n, "General protection fault.");
[f761f1eb]134}
135
[214ec25c]136static void ss_fault(unsigned int n __attribute__((unused)), istate_t *istate)
[6de2480e]137{
[f651e80]138 fault_if_from_uspace(istate, "Stack fault.");
[62baed17]139 panic_badtrap(istate, n, "Stack fault.");
[6de2480e]140}
141
[214ec25c]142static void simd_fp_exception(unsigned int n __attribute__((unused)), istate_t *istate)
[3b05862f]143{
[7f1c620]144 uint32_t mxcsr;
[da1bafb]145 asm volatile (
[1433ecda]146 "stmxcsr %[mxcsr]\n"
147 : [mxcsr] "=m" (mxcsr)
[3b05862f]148 );
[a35b458]149
[7e752b2]150 fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR=%#0" PRIx32 ".",
151 mxcsr);
152 panic_badtrap(istate, n, "SIMD FP exception");
[3b05862f]153}
154
[214ec25c]155static void nm_fault(unsigned int n __attribute__((unused)),
[da1bafb]156 istate_t *istate __attribute__((unused)))
[6a27d63]157{
[da1bafb]158#ifdef CONFIG_FPU_LAZY
[b49f4ae]159 scheduler_fpu_lazy_request();
160#else
[f651e80]161 fault_if_from_uspace(istate, "FPU fault.");
[62baed17]162 panic_badtrap(istate, n, "FPU fault.");
[b49f4ae]163#endif
[6a27d63]164}
165
[cea12e9]166#ifdef CONFIG_SMP
[214ec25c]167static void tlb_shootdown_ipi(unsigned int n __attribute__((unused)),
[da1bafb]168 istate_t *istate __attribute__((unused)))
[f761f1eb]169{
[2a103b5]170 pic_ops->eoi(0);
[cea12e9]171 tlb_shootdown_ipi_recv();
[f761f1eb]172}
[cea12e9]173#endif
[f761f1eb]174
[cea12e9]175/** Handler of IRQ exceptions */
[214ec25c]176static void irq_interrupt(unsigned int n, istate_t *istate __attribute__((unused)))
[169587a]177{
[63e27ef]178 assert(n >= IVT_IRQBASE);
[a35b458]179
[214ec25c]180 unsigned int inum = n - IVT_IRQBASE;
[7bcfbbc]181 bool ack = false;
[63e27ef]182 assert(inum < IRQ_COUNT);
[f6cf76f]183 assert(inum != IRQ_PIC1);
[a35b458]184
[cea12e9]185 irq_t *irq = irq_dispatch_and_lock(inum);
186 if (irq) {
187 /*
188 * The IRQ handler was found.
189 */
[a35b458]190
[7bcfbbc]191 if (irq->preack) {
192 /* Send EOI before processing the interrupt */
[2a103b5]193 pic_ops->eoi(inum);
[7bcfbbc]194 ack = true;
195 }
[6cd9aa6]196 irq->handler(irq);
[da1bafb]197 irq_spinlock_unlock(&irq->lock, false);
[cea12e9]198 } else {
199#ifdef CONFIG_DEBUG
[fd67c9f]200 log(LF_ARCH, LVL_DEBUG, "cpu%u: unhandled IRQ %u", CPU->id,
201 inum);
[cea12e9]202#endif
203 }
[a35b458]204
[7bcfbbc]205 if (!ack)
[2a103b5]206 pic_ops->eoi(inum);
[cea12e9]207}
208
[f6cf76f]209static void pic_spurious(unsigned int n, istate_t *istate)
210{
[fd67c9f]211 unsigned int inum = n - IVT_IRQBASE;
[2a103b5]212 if (!pic_ops->is_spurious(inum)) {
[fd67c9f]213 /* This is actually not a spurious IRQ, so proceed as usual. */
214 irq_interrupt(n, istate);
215 return;
216 }
[2a103b5]217 pic_ops->handle_spurious(n);
[f6cf76f]218#ifdef CONFIG_DEBUG
[fd67c9f]219 log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt %u", CPU->id,
220 inum);
[f6cf76f]221#endif
222}
223
[cea12e9]224void interrupt_init(void)
225{
[b3b7e14a]226 unsigned int i;
[a35b458]227
[cea12e9]228 for (i = 0; i < IVT_ITEMS; i++)
[b3b7e14a]229 exc_register(i, "null", false, (iroutine_t) null_interrupt);
[a35b458]230
[cea12e9]231 for (i = 0; i < IRQ_COUNT; i++) {
[f6cf76f]232 if ((i != IRQ_PIC0_SPUR) && (i != IRQ_PIC1_SPUR) &&
233 (i != IRQ_PIC1))
[b3b7e14a]234 exc_register(IVT_IRQBASE + i, "irq", true,
235 (iroutine_t) irq_interrupt);
[cea12e9]236 }
[a35b458]237
[4b0206c]238 exc_register(VECTOR_DE, "de_fault", true, (iroutine_t) de_fault);
[ae89656]239 exc_register(VECTOR_DB, "db_exc", true, (iroutine_t) db_exception);
[4b0206c]240 exc_register(VECTOR_NM, "nm_fault", true, (iroutine_t) nm_fault);
241 exc_register(VECTOR_SS, "ss_fault", true, (iroutine_t) ss_fault);
242 exc_register(VECTOR_GP, "gp_fault", true, (iroutine_t) gp_fault);
243 exc_register(VECTOR_XM, "simd_fp", true, (iroutine_t) simd_fp_exception);
[f6cf76f]244 exc_register(VECTOR_PIC0_SPUR, "pic0_spurious", true,
245 (iroutine_t) pic_spurious);
246 exc_register(VECTOR_PIC1_SPUR, "pic1_spurious", true,
247 (iroutine_t) pic_spurious);
[a35b458]248
[cea12e9]249#ifdef CONFIG_SMP
[b3b7e14a]250 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
251 (iroutine_t) tlb_shootdown_ipi);
[cea12e9]252#endif
[169587a]253}
254
[3222efd]255/** @}
[b45c443]256 */
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