source: mainline/kernel/arch/ia32/src/ia32.c@ 0b5f9fa

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0b5f9fa was 0b5f9fa, checked in by Martin Decky <martin@…>, 17 years ago

remove memory_print_map(), as it duplicates functionality of physmem_print()

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch.h>
36
37#include <arch/types.h>
38
39#include <arch/pm.h>
40
41#include <arch/drivers/ega.h>
42#include <arch/drivers/vesa.h>
43#include <genarch/kbd/i8042.h>
44#include <arch/drivers/i8254.h>
45#include <arch/drivers/i8259.h>
46
47#include <arch/context.h>
48
49#include <config.h>
50
51#include <arch/interrupt.h>
52#include <arch/asm.h>
53#include <genarch/acpi/acpi.h>
54
55#include <arch/bios/bios.h>
56
57#include <arch/mm/memory_init.h>
58#include <interrupt.h>
59#include <ddi/irq.h>
60#include <arch/debugger.h>
61#include <proc/thread.h>
62#include <syscall/syscall.h>
63#include <console/console.h>
64#include <ddi/device.h>
65
66#ifdef CONFIG_SMP
67#include <arch/smp/apic.h>
68#endif
69
70void arch_pre_mm_init(void)
71{
72 pm_init();
73
74 if (config.cpu_active == 1) {
75 interrupt_init();
76 bios_init();
77
78 /* PIC */
79 i8259_init();
80 }
81}
82
83void arch_post_mm_init(void)
84{
85 if (config.cpu_active == 1) {
86 /* Initialize IRQ routing */
87 irq_init(IRQ_COUNT, IRQ_COUNT);
88
89 /* hard clock */
90 i8254_init();
91
92#ifdef CONFIG_FB
93 if (vesa_present())
94 vesa_init();
95 else
96#endif
97 ega_init(); /* video */
98
99 /* Enable debugger */
100 debugger_init();
101 /* Merge all memory zones to 1 big zone */
102 zone_merge_all();
103 }
104}
105
106void arch_post_cpu_init()
107{
108#ifdef CONFIG_SMP
109 if (config.cpu_active > 1) {
110 l_apic_init();
111 l_apic_debug();
112 }
113#endif
114}
115
116void arch_pre_smp_init(void)
117{
118 if (config.cpu_active == 1) {
119#ifdef CONFIG_SMP
120 acpi_init();
121#endif /* CONFIG_SMP */
122 }
123}
124
125void arch_post_smp_init(void)
126{
127 devno_t kbd = device_assign_devno();
128 devno_t mouse = device_assign_devno();
129 /* keyboard controller */
130 i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE);
131}
132
133void calibrate_delay_loop(void)
134{
135 i8254_calibrate_delay_loop();
136 if (config.cpu_active == 1) {
137 /*
138 * This has to be done only on UP.
139 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
140 */
141 i8254_normal_operation();
142 }
143}
144
145/** Set thread-local-storage pointer
146 *
147 * TLS pointer is set in GS register. That means, the GS contains
148 * selector, and the descriptor->base is the correct address.
149 */
150unative_t sys_tls_set(unative_t addr)
151{
152 THREAD->arch.tls = addr;
153 set_tls_desc(addr);
154
155 return 0;
156}
157
158/** Acquire console back for kernel
159 *
160 */
161void arch_grab_console(void)
162{
163 i8042_grab();
164}
165/** Return console to userspace
166 *
167 */
168void arch_release_console(void)
169{
170 i8042_release();
171}
172
173/** @}
174 */
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