source: mainline/kernel/arch/ia32/src/ia32.c@ eae4e8f

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since eae4e8f was eae4e8f, checked in by Jakub Jermar <jakub@…>, 16 years ago

Fix missing includes.

  • Property mode set to 100644
File size: 5.6 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[deca67b]3 * Copyright (c) 2009 Jiri Svoboda
4 * Copyright (c) 2009 Martin Decky
[f761f1eb]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[06e1e95]31/** @addtogroup ia32
[b45c443]32 * @{
33 */
34/** @file
35 */
36
[f761f1eb]37#include <arch.h>
38
39#include <arch/types.h>
40
41#include <arch/pm.h>
42
[5d8d71e]43#include <genarch/multiboot/multiboot.h>
[91825d90]44#include <genarch/drivers/legacy/ia32/io.h>
[f245145]45#include <genarch/drivers/ega/ega.h>
[80d31883]46#include <arch/drivers/vesa.h>
[411b6a6]47#include <genarch/drivers/i8042/i8042.h>
48#include <genarch/kbrd/kbrd.h>
[80d31883]49#include <arch/drivers/i8254.h>
50#include <arch/drivers/i8259.h>
[f761f1eb]51
52#include <arch/context.h>
53
54#include <config.h>
55
56#include <arch/interrupt.h>
[ad36bd6]57#include <arch/asm.h>
[e16e036a]58#include <genarch/acpi/acpi.h>
[9c0a9b3]59
60#include <arch/bios/bios.h>
61
[fcfac420]62#include <interrupt.h>
[cea12e9]63#include <ddi/irq.h>
[23d22eb]64#include <arch/debugger.h>
[281b607]65#include <proc/thread.h>
66#include <syscall/syscall.h>
[41d33ac]67#include <console/console.h>
[4c7257b]68#include <sysinfo/sysinfo.h>
[deca67b]69#include <arch/boot/boot.h>
[eae4e8f]70#include <memstr.h>
[ad36bd6]71
[26678e5]72#ifdef CONFIG_SMP
73#include <arch/smp/apic.h>
74#endif
75
[5d8d71e]76/** Perform ia32-specific initialization before main_bsp() is called.
[deca67b]77 *
78 * @param signature Should contain the multiboot signature.
79 * @param mi Pointer to the multiboot information structure.
80 */
[5d8d71e]81void arch_pre_main(uint32_t signature, const multiboot_info_t *mi)
[deca67b]82{
[5d8d71e]83 /* Parse multiboot information obtained from the bootloader. */
[c2417bc]84 multiboot_info_parse(signature, mi);
[deca67b]85
86#ifdef CONFIG_SMP
87 /* Copy AP bootstrap routines below 1 MB. */
88 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
89 (size_t) &_hardcoded_unmapped_size);
90#endif
91}
92
[f07bba5]93void arch_pre_mm_init(void)
[f761f1eb]94{
95 pm_init();
96
97 if (config.cpu_active == 1) {
[cea12e9]98 interrupt_init();
[dba84ff]99 bios_init();
[5dce48b9]100
[cea12e9]101 /* PIC */
102 i8259_init();
[f761f1eb]103 }
104}
105
[6ba143d]106void arch_post_mm_init(void)
[7eade45]107{
[425913b]108 if (config.cpu_active == 1) {
[cea12e9]109 /* Initialize IRQ routing */
110 irq_init(IRQ_COUNT, IRQ_COUNT);
111
112 /* hard clock */
113 i8254_init();
[ec944b1]114
[a71c158]115#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
116 bool vesa = false;
117#endif
118
[22cf454d]119#ifdef CONFIG_FB
[a71c158]120 vesa = vesa_init();
[22cf454d]121#endif
[a71c158]122
[ec944b1]123#ifdef CONFIG_EGA
[a71c158]124 if (!vesa) {
125 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
126 if (egadev)
127 stdout_wire(egadev);
128 }
[ec944b1]129#endif
[22cf454d]130
[23d22eb]131 /* Enable debugger */
132 debugger_init();
[381465e]133 /* Merge all memory zones to 1 big zone */
134 zone_merge_all();
[babcb148]135 }
136}
137
[26678e5]138void arch_post_cpu_init()
139{
140#ifdef CONFIG_SMP
141 if (config.cpu_active > 1) {
142 l_apic_init();
143 l_apic_debug();
144 }
145#endif
146}
147
[7453929]148void arch_pre_smp_init(void)
[babcb148]149{
150 if (config.cpu_active == 1) {
[f619ec11]151#ifdef CONFIG_SMP
[85bfdcc8]152 acpi_init();
[f619ec11]153#endif /* CONFIG_SMP */
[425913b]154 }
[7eade45]155}
156
[7453929]157void arch_post_smp_init(void)
158{
[2a34e4c]159#ifdef CONFIG_PC_KBD
[411b6a6]160 /*
[2a34e4c]161 * Initialize the i8042 controller. Then initialize the keyboard
162 * module and connect it to i8042. Enable keyboard interrupts.
[411b6a6]163 */
[c2417bc]164 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
165 if (i8042_instance) {
166 kbrd_instance_t *kbrd_instance = kbrd_init();
167 if (kbrd_instance) {
168 indev_t *sink = stdin_wire();
169 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
170 i8042_wire(i8042_instance, kbrd);
171 trap_virtual_enable_irqs(1 << IRQ_KBD);
172 }
[2a34e4c]173 }
174
[4c7257b]175 /*
176 * This is the necessary evil until the userspace driver is entirely
177 * self-sufficient.
178 */
179 sysinfo_set_item_val("kbd", NULL, true);
180 sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
[ff685c9]181 sysinfo_set_item_val("kbd.address.physical", NULL,
182 (uintptr_t) I8042_BASE);
183 sysinfo_set_item_val("kbd.address.kernel", NULL,
184 (uintptr_t) I8042_BASE);
[2a34e4c]185#endif
[7453929]186}
187
[f761f1eb]188void calibrate_delay_loop(void)
189{
190 i8254_calibrate_delay_loop();
[f701b236]191 if (config.cpu_active == 1) {
192 /*
193 * This has to be done only on UP.
194 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
195 */
196 i8254_normal_operation();
197 }
[f761f1eb]198}
[281b607]199
[e1be3b6]200/** Set thread-local-storage pointer
[281b607]201 *
[3b712407]202 * TLS pointer is set in GS register. That means, the GS contains
203 * selector, and the descriptor->base is the correct address.
[281b607]204 */
[7f1c620]205unative_t sys_tls_set(unative_t addr)
[281b607]206{
[a6d4ceb]207 THREAD->arch.tls = addr;
[281b607]208 set_tls_desc(addr);
[a71c158]209
[281b607]210 return 0;
211}
[41d33ac]212
[6da1013f]213/** Construct function pointer
214 *
215 * @param fptr function pointer structure
216 * @param addr function address
217 * @param caller calling function address
218 *
219 * @return address of the function pointer
220 *
221 */
222void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
223{
224 return addr;
225}
226
[149d14e5]227void arch_reboot(void)
228{
229#ifdef CONFIG_PC_KBD
230 i8042_cpu_reset((i8042_t *) I8042_BASE);
231#endif
232}
233
[06e1e95]234/** @}
[b45c443]235 */
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