source: mainline/kernel/arch/ia32/src/ia32.c@ b44939b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b44939b was 06e1e95, checked in by Jakub Jermar <jakub@…>, 19 years ago

C99 compliant header guards (hopefully) everywhere in the kernel.
Formatting and indentation changes.
Small improvements in sparc64.

  • Property mode set to 100644
File size: 3.6 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch.h>
36
37#include <arch/types.h>
38#include <typedefs.h>
39
40#include <arch/pm.h>
41
[018f95a]42#include <arch/drivers/ega.h>
[80d31883]43#include <arch/drivers/vesa.h>
[287920f]44#include <genarch/kbd/i8042.h>
[80d31883]45#include <arch/drivers/i8254.h>
46#include <arch/drivers/i8259.h>
[f761f1eb]47
48#include <arch/context.h>
49
50#include <config.h>
51
52#include <arch/interrupt.h>
[ad36bd6]53#include <arch/asm.h>
[e16e036a]54#include <genarch/acpi/acpi.h>
[9c0a9b3]55
56#include <arch/bios/bios.h>
57
[1e9a463]58#include <arch/mm/memory_init.h>
[fcfac420]59#include <interrupt.h>
[23d22eb]60#include <arch/debugger.h>
[281b607]61#include <proc/thread.h>
62#include <syscall/syscall.h>
[41d33ac]63#include <console/console.h>
[ad36bd6]64
[f07bba5]65void arch_pre_mm_init(void)
[f761f1eb]66{
67 pm_init();
68
69 if (config.cpu_active == 1) {
[dba84ff]70 bios_init();
[76cec1e]71 i8259_init(); /* PIC */
[f761f1eb]72 i8254_init(); /* hard clock */
[5dce48b9]73
[25d7709]74 exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall);
[169587a]75
[5f85c91]76 #ifdef CONFIG_SMP
[fcfac420]77 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
[25d7709]78 (iroutine) tlb_shootdown_ipi);
[5f85c91]79 #endif /* CONFIG_SMP */
[f761f1eb]80 }
81}
82
[6ba143d]83void arch_post_mm_init(void)
[7eade45]84{
[425913b]85 if (config.cpu_active == 1) {
[22cf454d]86
87#ifdef CONFIG_FB
[381465e]88 if (vesa_present())
89 vesa_init();
[22cf454d]90 else
91#endif
[381465e]92 ega_init(); /* video */
[22cf454d]93
94
[23d22eb]95 /* Enable debugger */
96 debugger_init();
[381465e]97 /* Merge all memory zones to 1 big zone */
98 zone_merge_all();
[babcb148]99 }
100}
101
[7453929]102void arch_pre_smp_init(void)
[babcb148]103{
104 if (config.cpu_active == 1) {
[1e9a463]105 memory_print_map();
106
[5f85c91]107 #ifdef CONFIG_SMP
[85bfdcc8]108 acpi_init();
[5f85c91]109 #endif /* CONFIG_SMP */
[425913b]110 }
[7eade45]111}
112
[7453929]113void arch_post_smp_init(void)
114{
[a83a802]115 i8042_init(); /* keyboard controller */
[7453929]116}
117
[f761f1eb]118void calibrate_delay_loop(void)
119{
120 i8254_calibrate_delay_loop();
[f701b236]121 if (config.cpu_active == 1) {
122 /*
123 * This has to be done only on UP.
124 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
125 */
126 i8254_normal_operation();
127 }
[f761f1eb]128}
[281b607]129
[e1be3b6]130/** Set thread-local-storage pointer
[281b607]131 *
[3b712407]132 * TLS pointer is set in GS register. That means, the GS contains
133 * selector, and the descriptor->base is the correct address.
[281b607]134 */
[7f1c620]135unative_t sys_tls_set(unative_t addr)
[281b607]136{
[a6d4ceb]137 THREAD->arch.tls = addr;
[281b607]138 set_tls_desc(addr);
139
140 return 0;
141}
[41d33ac]142
143/** Acquire console back for kernel
144 *
145 */
146void arch_grab_console(void)
147{
148 i8042_grab();
149}
150/** Return console to userspace
151 *
152 */
153void arch_release_console(void)
154{
155 i8042_release();
156}
[b45c443]157
[06e1e95]158/** @}
[b45c443]159 */
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