[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[deca67b] | 3 | * Copyright (c) 2009 Jiri Svoboda
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| 4 | * Copyright (c) 2009 Martin Decky
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[f761f1eb] | 5 | * All rights reserved.
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| 6 | *
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| 7 | * Redistribution and use in source and binary forms, with or without
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| 8 | * modification, are permitted provided that the following conditions
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| 9 | * are met:
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| 10 | *
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| 11 | * - Redistributions of source code must retain the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer.
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| 13 | * - Redistributions in binary form must reproduce the above copyright
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| 14 | * notice, this list of conditions and the following disclaimer in the
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| 15 | * documentation and/or other materials provided with the distribution.
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| 16 | * - The name of the author may not be used to endorse or promote products
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| 17 | * derived from this software without specific prior written permission.
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| 18 | *
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 29 | */
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| 30 |
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[06e1e95] | 31 | /** @addtogroup ia32
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[b45c443] | 32 | * @{
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| 33 | */
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| 34 | /** @file
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| 35 | */
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| 36 |
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[f761f1eb] | 37 | #include <arch.h>
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[d99c1d2] | 38 | #include <typedefs.h>
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[d8db519] | 39 | #include <errno.h>
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| 40 | #include <memstr.h>
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[fcfac420] | 41 | #include <interrupt.h>
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[41d33ac] | 42 | #include <console/console.h>
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[d8db519] | 43 | #include <syscall/syscall.h>
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[4c7257b] | 44 | #include <sysinfo/sysinfo.h>
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[d8db519] | 45 | #include <arch/bios/bios.h>
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[deca67b] | 46 | #include <arch/boot/boot.h>
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[d8db519] | 47 | #include <arch/debugger.h>
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| 48 | #include <arch/drivers/i8254.h>
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| 49 | #include <arch/drivers/i8259.h>
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| 50 | #include <genarch/acpi/acpi.h>
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| 51 | #include <genarch/drivers/ega/ega.h>
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| 52 | #include <genarch/drivers/i8042/i8042.h>
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| 53 | #include <genarch/drivers/legacy/ia32/io.h>
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| 54 | #include <genarch/fb/bfb.h>
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| 55 | #include <genarch/kbrd/kbrd.h>
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| 56 | #include <genarch/multiboot/multiboot.h>
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| 57 | #include <genarch/multiboot/multiboot2.h>
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[ad36bd6] | 58 |
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[26678e5] | 59 | #ifdef CONFIG_SMP
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| 60 | #include <arch/smp/apic.h>
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| 61 | #endif
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| 62 |
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[5d8d71e] | 63 | /** Perform ia32-specific initialization before main_bsp() is called.
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[deca67b] | 64 | *
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[1f5c9c96] | 65 | * @param signature Multiboot signature.
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| 66 | * @param info Multiboot information structure.
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| 67 | *
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[deca67b] | 68 | */
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[1f5c9c96] | 69 | void arch_pre_main(uint32_t signature, void *info)
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[deca67b] | 70 | {
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[5d8d71e] | 71 | /* Parse multiboot information obtained from the bootloader. */
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[1f5c9c96] | 72 | multiboot_info_parse(signature, (multiboot_info_t *) info);
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| 73 | multiboot2_info_parse(signature, (multiboot2_info_t *) info);
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[deca67b] | 74 |
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| 75 | #ifdef CONFIG_SMP
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| 76 | /* Copy AP bootstrap routines below 1 MB. */
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| 77 | memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
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| 78 | (size_t) &_hardcoded_unmapped_size);
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| 79 | #endif
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| 80 | }
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| 81 |
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[f07bba5] | 82 | void arch_pre_mm_init(void)
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[f761f1eb] | 83 | {
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| 84 | pm_init();
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| 85 |
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| 86 | if (config.cpu_active == 1) {
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[cea12e9] | 87 | interrupt_init();
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[dba84ff] | 88 | bios_init();
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[5dce48b9] | 89 |
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[cea12e9] | 90 | /* PIC */
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| 91 | i8259_init();
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[f761f1eb] | 92 | }
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| 93 | }
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| 94 |
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[6ba143d] | 95 | void arch_post_mm_init(void)
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[7eade45] | 96 | {
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[425913b] | 97 | if (config.cpu_active == 1) {
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[cea12e9] | 98 | /* Initialize IRQ routing */
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| 99 | irq_init(IRQ_COUNT, IRQ_COUNT);
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| 100 |
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| 101 | /* hard clock */
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| 102 | i8254_init();
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[ec944b1] | 103 |
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[a71c158] | 104 | #if (defined(CONFIG_FB) || defined(CONFIG_EGA))
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[1f5c9c96] | 105 | bool bfb = false;
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[a71c158] | 106 | #endif
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| 107 |
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[22cf454d] | 108 | #ifdef CONFIG_FB
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[1f5c9c96] | 109 | bfb = bfb_init();
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[22cf454d] | 110 | #endif
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[a71c158] | 111 |
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[ec944b1] | 112 | #ifdef CONFIG_EGA
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[1f5c9c96] | 113 | if (!bfb) {
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[a71c158] | 114 | outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
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| 115 | if (egadev)
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| 116 | stdout_wire(egadev);
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| 117 | }
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[ec944b1] | 118 | #endif
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[22cf454d] | 119 |
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[23d22eb] | 120 | /* Enable debugger */
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| 121 | debugger_init();
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[381465e] | 122 | /* Merge all memory zones to 1 big zone */
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| 123 | zone_merge_all();
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[babcb148] | 124 | }
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| 125 | }
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| 126 |
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[26678e5] | 127 | void arch_post_cpu_init()
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| 128 | {
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| 129 | #ifdef CONFIG_SMP
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[49eb681] | 130 | if (config.cpu_active > 1) {
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[26678e5] | 131 | l_apic_init();
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| 132 | l_apic_debug();
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| 133 | }
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| 134 | #endif
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| 135 | }
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| 136 |
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[7453929] | 137 | void arch_pre_smp_init(void)
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[babcb148] | 138 | {
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| 139 | if (config.cpu_active == 1) {
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[f619ec11] | 140 | #ifdef CONFIG_SMP
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[85bfdcc8] | 141 | acpi_init();
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[f619ec11] | 142 | #endif /* CONFIG_SMP */
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[425913b] | 143 | }
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[7eade45] | 144 | }
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| 145 |
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[7453929] | 146 | void arch_post_smp_init(void)
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| 147 | {
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[eff1f033] | 148 | /* Currently the only supported platform for ia32 is 'pc'. */
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| 149 | static const char *platform = "pc";
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| 150 |
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| 151 | sysinfo_set_item_data("platform", NULL, (void *) platform,
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| 152 | str_size(platform));
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| 153 |
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[2a34e4c] | 154 | #ifdef CONFIG_PC_KBD
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[411b6a6] | 155 | /*
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[2a34e4c] | 156 | * Initialize the i8042 controller. Then initialize the keyboard
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| 157 | * module and connect it to i8042. Enable keyboard interrupts.
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[411b6a6] | 158 | */
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[c2417bc] | 159 | i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
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| 160 | if (i8042_instance) {
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| 161 | kbrd_instance_t *kbrd_instance = kbrd_init();
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| 162 | if (kbrd_instance) {
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| 163 | indev_t *sink = stdin_wire();
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| 164 | indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
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| 165 | i8042_wire(i8042_instance, kbrd);
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| 166 | trap_virtual_enable_irqs(1 << IRQ_KBD);
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[385a3d6] | 167 | trap_virtual_enable_irqs(1 << IRQ_MOUSE);
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[c2417bc] | 168 | }
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[2a34e4c] | 169 | }
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| 170 | #endif
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[849ed54] | 171 |
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[acc7ce4] | 172 | if (irqs_info != NULL)
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| 173 | sysinfo_set_item_val(irqs_info, NULL, true);
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[7453929] | 174 | }
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| 175 |
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[f761f1eb] | 176 | void calibrate_delay_loop(void)
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| 177 | {
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| 178 | i8254_calibrate_delay_loop();
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[f701b236] | 179 | if (config.cpu_active == 1) {
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| 180 | /*
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| 181 | * This has to be done only on UP.
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| 182 | * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
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| 183 | */
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| 184 | i8254_normal_operation();
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| 185 | }
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[f761f1eb] | 186 | }
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[281b607] | 187 |
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[e1be3b6] | 188 | /** Set thread-local-storage pointer
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[281b607] | 189 | *
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[3b712407] | 190 | * TLS pointer is set in GS register. That means, the GS contains
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| 191 | * selector, and the descriptor->base is the correct address.
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[281b607] | 192 | */
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[d8db519] | 193 | sysarg_t sys_tls_set(uintptr_t addr)
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[281b607] | 194 | {
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[a6d4ceb] | 195 | THREAD->arch.tls = addr;
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[281b607] | 196 | set_tls_desc(addr);
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[a71c158] | 197 |
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[d8db519] | 198 | return EOK;
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[281b607] | 199 | }
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[41d33ac] | 200 |
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[6da1013f] | 201 | /** Construct function pointer
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| 202 | *
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| 203 | * @param fptr function pointer structure
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| 204 | * @param addr function address
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| 205 | * @param caller calling function address
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| 206 | *
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| 207 | * @return address of the function pointer
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| 208 | *
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| 209 | */
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| 210 | void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
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| 211 | {
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| 212 | return addr;
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| 213 | }
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| 214 |
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[149d14e5] | 215 | void arch_reboot(void)
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| 216 | {
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| 217 | #ifdef CONFIG_PC_KBD
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| 218 | i8042_cpu_reset((i8042_t *) I8042_BASE);
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| 219 | #endif
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| 220 | }
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| 221 |
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[3a2f8aa] | 222 | void irq_initialize_arch(irq_t *irq)
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| 223 | {
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| 224 | (void) irq;
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| 225 | }
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| 226 |
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[06e1e95] | 227 | /** @}
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[b45c443] | 228 | */
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