source: mainline/kernel/arch/ia32/src/ia32.c@ 59fb782

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 59fb782 was 4a5ba372, checked in by Jakub Jermar <jakub@…>, 13 years ago

Remove the unmaintained ia32 and amd64 kernel debugger.

  • Property mode set to 100644
File size: 5.5 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[deca67b]3 * Copyright (c) 2009 Jiri Svoboda
4 * Copyright (c) 2009 Martin Decky
[f761f1eb]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[06e1e95]31/** @addtogroup ia32
[b45c443]32 * @{
33 */
34/** @file
35 */
36
[f761f1eb]37#include <arch.h>
[d99c1d2]38#include <typedefs.h>
[d8db519]39#include <errno.h>
40#include <memstr.h>
[fcfac420]41#include <interrupt.h>
[41d33ac]42#include <console/console.h>
[d8db519]43#include <syscall/syscall.h>
[4c7257b]44#include <sysinfo/sysinfo.h>
[d8db519]45#include <arch/bios/bios.h>
[deca67b]46#include <arch/boot/boot.h>
[d8db519]47#include <arch/drivers/i8254.h>
48#include <arch/drivers/i8259.h>
49#include <genarch/acpi/acpi.h>
50#include <genarch/drivers/ega/ega.h>
51#include <genarch/drivers/i8042/i8042.h>
52#include <genarch/drivers/legacy/ia32/io.h>
53#include <genarch/fb/bfb.h>
54#include <genarch/kbrd/kbrd.h>
55#include <genarch/multiboot/multiboot.h>
56#include <genarch/multiboot/multiboot2.h>
[ad36bd6]57
[26678e5]58#ifdef CONFIG_SMP
59#include <arch/smp/apic.h>
60#endif
61
[5d8d71e]62/** Perform ia32-specific initialization before main_bsp() is called.
[deca67b]63 *
[1f5c9c96]64 * @param signature Multiboot signature.
65 * @param info Multiboot information structure.
66 *
[deca67b]67 */
[1f5c9c96]68void arch_pre_main(uint32_t signature, void *info)
[deca67b]69{
[5d8d71e]70 /* Parse multiboot information obtained from the bootloader. */
[1f5c9c96]71 multiboot_info_parse(signature, (multiboot_info_t *) info);
72 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
[deca67b]73
74#ifdef CONFIG_SMP
75 /* Copy AP bootstrap routines below 1 MB. */
76 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
77 (size_t) &_hardcoded_unmapped_size);
78#endif
79}
80
[f07bba5]81void arch_pre_mm_init(void)
[f761f1eb]82{
83 pm_init();
84
85 if (config.cpu_active == 1) {
[cea12e9]86 interrupt_init();
[dba84ff]87 bios_init();
[5dce48b9]88
[cea12e9]89 /* PIC */
90 i8259_init();
[f761f1eb]91 }
92}
93
[6ba143d]94void arch_post_mm_init(void)
[7eade45]95{
[425913b]96 if (config.cpu_active == 1) {
[cea12e9]97 /* Initialize IRQ routing */
98 irq_init(IRQ_COUNT, IRQ_COUNT);
99
100 /* hard clock */
101 i8254_init();
[ec944b1]102
[a71c158]103#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
[1f5c9c96]104 bool bfb = false;
[a71c158]105#endif
106
[22cf454d]107#ifdef CONFIG_FB
[1f5c9c96]108 bfb = bfb_init();
[22cf454d]109#endif
[a71c158]110
[ec944b1]111#ifdef CONFIG_EGA
[1f5c9c96]112 if (!bfb) {
[a71c158]113 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
114 if (egadev)
115 stdout_wire(egadev);
116 }
[ec944b1]117#endif
[22cf454d]118
[381465e]119 /* Merge all memory zones to 1 big zone */
120 zone_merge_all();
[babcb148]121 }
122}
123
[26678e5]124void arch_post_cpu_init()
125{
126#ifdef CONFIG_SMP
[49eb681]127 if (config.cpu_active > 1) {
[26678e5]128 l_apic_init();
129 l_apic_debug();
130 }
131#endif
132}
133
[7453929]134void arch_pre_smp_init(void)
[babcb148]135{
136 if (config.cpu_active == 1) {
[f619ec11]137#ifdef CONFIG_SMP
[85bfdcc8]138 acpi_init();
[f619ec11]139#endif /* CONFIG_SMP */
[425913b]140 }
[7eade45]141}
142
[7453929]143void arch_post_smp_init(void)
144{
[eff1f033]145 /* Currently the only supported platform for ia32 is 'pc'. */
146 static const char *platform = "pc";
147
148 sysinfo_set_item_data("platform", NULL, (void *) platform,
149 str_size(platform));
150
[2a34e4c]151#ifdef CONFIG_PC_KBD
[411b6a6]152 /*
[2a34e4c]153 * Initialize the i8042 controller. Then initialize the keyboard
154 * module and connect it to i8042. Enable keyboard interrupts.
[411b6a6]155 */
[c2417bc]156 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
157 if (i8042_instance) {
158 kbrd_instance_t *kbrd_instance = kbrd_init();
159 if (kbrd_instance) {
160 indev_t *sink = stdin_wire();
161 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
162 i8042_wire(i8042_instance, kbrd);
163 trap_virtual_enable_irqs(1 << IRQ_KBD);
[385a3d6]164 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
[c2417bc]165 }
[2a34e4c]166 }
167#endif
[849ed54]168
[acc7ce4]169 if (irqs_info != NULL)
170 sysinfo_set_item_val(irqs_info, NULL, true);
[7453929]171}
172
[f761f1eb]173void calibrate_delay_loop(void)
174{
175 i8254_calibrate_delay_loop();
[f701b236]176 if (config.cpu_active == 1) {
177 /*
178 * This has to be done only on UP.
179 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
180 */
181 i8254_normal_operation();
182 }
[f761f1eb]183}
[281b607]184
[e1be3b6]185/** Set thread-local-storage pointer
[281b607]186 *
[3b712407]187 * TLS pointer is set in GS register. That means, the GS contains
188 * selector, and the descriptor->base is the correct address.
[281b607]189 */
[d8db519]190sysarg_t sys_tls_set(uintptr_t addr)
[281b607]191{
[a6d4ceb]192 THREAD->arch.tls = addr;
[281b607]193 set_tls_desc(addr);
[a71c158]194
[d8db519]195 return EOK;
[281b607]196}
[41d33ac]197
[6da1013f]198/** Construct function pointer
199 *
200 * @param fptr function pointer structure
201 * @param addr function address
202 * @param caller calling function address
203 *
204 * @return address of the function pointer
205 *
206 */
207void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
208{
209 return addr;
210}
211
[149d14e5]212void arch_reboot(void)
213{
214#ifdef CONFIG_PC_KBD
215 i8042_cpu_reset((i8042_t *) I8042_BASE);
216#endif
217}
218
[3a2f8aa]219void irq_initialize_arch(irq_t *irq)
220{
221 (void) irq;
222}
223
[06e1e95]224/** @}
[b45c443]225 */
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