source: mainline/kernel/arch/ia32/src/ia32.c@ 3daba42e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3daba42e was 3daba42e, checked in by Jakub Jermar <jakub@…>, 6 years ago

Always chain pic0 and pic1 using IRQ 2

  • Property mode set to 100644
File size: 6.9 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[deca67b]3 * Copyright (c) 2009 Jiri Svoboda
4 * Copyright (c) 2009 Martin Decky
[f761f1eb]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[c5429fe]31/** @addtogroup kernel_ia32
[b45c443]32 * @{
33 */
34/** @file
35 */
36
[f761f1eb]37#include <arch.h>
[36df4109]38#include <arch/arch.h>
[83dab11]39#include <stdint.h>
[d8db519]40#include <errno.h>
[44a7ee5]41#include <mem.h>
[fcfac420]42#include <interrupt.h>
[41d33ac]43#include <console/console.h>
[d8db519]44#include <syscall/syscall.h>
[4c7257b]45#include <sysinfo/sysinfo.h>
[d8db519]46#include <arch/bios/bios.h>
[deca67b]47#include <arch/boot/boot.h>
[d8db519]48#include <arch/drivers/i8254.h>
49#include <genarch/acpi/acpi.h>
50#include <genarch/drivers/ega/ega.h>
51#include <genarch/drivers/i8042/i8042.h>
[87a5796]52#include <genarch/drivers/i8259/i8259.h>
[3296df5]53#include <genarch/drivers/ns16550/ns16550.h>
[d8db519]54#include <genarch/drivers/legacy/ia32/io.h>
55#include <genarch/fb/bfb.h>
56#include <genarch/kbrd/kbrd.h>
[3296df5]57#include <genarch/srln/srln.h>
[d8db519]58#include <genarch/multiboot/multiboot.h>
59#include <genarch/multiboot/multiboot2.h>
[d6f9fff]60#include <arch/pm.h>
61#include <arch/vreg.h>
[ad36bd6]62
[26678e5]63#ifdef CONFIG_SMP
64#include <arch/smp/apic.h>
65#endif
66
[36df4109]67static void ia32_pre_mm_init(void);
68static void ia32_post_mm_init(void);
69static void ia32_post_cpu_init(void);
70static void ia32_pre_smp_init(void);
71static void ia32_post_smp_init(void);
72
73arch_ops_t ia32_ops = {
74 .pre_mm_init = ia32_pre_mm_init,
75 .post_mm_init = ia32_post_mm_init,
76 .post_cpu_init = ia32_post_cpu_init,
77 .pre_smp_init = ia32_pre_smp_init,
78 .post_smp_init = ia32_post_smp_init,
79};
80
81arch_ops_t *arch_ops = &ia32_ops;
82
[5d8d71e]83/** Perform ia32-specific initialization before main_bsp() is called.
[deca67b]84 *
[1f5c9c96]85 * @param signature Multiboot signature.
86 * @param info Multiboot information structure.
87 *
[deca67b]88 */
[36df4109]89void ia32_pre_main(uint32_t signature, void *info)
[deca67b]90{
[5d8d71e]91 /* Parse multiboot information obtained from the bootloader. */
[1f5c9c96]92 multiboot_info_parse(signature, (multiboot_info_t *) info);
93 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
[a35b458]94
[deca67b]95#ifdef CONFIG_SMP
[bae43dc]96 size_t unmapped_size = (uintptr_t) unmapped_end - BOOT_OFFSET;
[deca67b]97 /* Copy AP bootstrap routines below 1 MB. */
[8a1afd2]98 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET, unmapped_size);
[deca67b]99#endif
100}
101
[36df4109]102void ia32_pre_mm_init(void)
[f761f1eb]103{
104 pm_init();
105
106 if (config.cpu_active == 1) {
[cea12e9]107 interrupt_init();
[dba84ff]108 bios_init();
[a35b458]109
[cea12e9]110 /* PIC */
[d1cbad5]111 i8259_init((i8259_t *) I8259_PIC0_BASE,
[3daba42e]112 (i8259_t *) I8259_PIC1_BASE, IVT_IRQBASE);
[bbb99f82]113
114 /*
115 * Set the enable/disable IRQs handlers.
116 * Set the End-of-Interrupt handler.
117 */
118 enable_irqs_function = pic_enable_irqs;
119 disable_irqs_function = pic_disable_irqs;
120 eoi_function = pic_eoi;
121 irqs_info = "i8259";
[f761f1eb]122 }
123}
124
[36df4109]125void ia32_post_mm_init(void)
[7eade45]126{
[d6f9fff]127 vreg_init();
128
[425913b]129 if (config.cpu_active == 1) {
[cea12e9]130 /* Initialize IRQ routing */
131 irq_init(IRQ_COUNT, IRQ_COUNT);
[a35b458]132
[cea12e9]133 /* hard clock */
134 i8254_init();
[a35b458]135
[a71c158]136#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
[1f5c9c96]137 bool bfb = false;
[a71c158]138#endif
[a35b458]139
[22cf454d]140#ifdef CONFIG_FB
[1f5c9c96]141 bfb = bfb_init();
[22cf454d]142#endif
[a35b458]143
[ec944b1]144#ifdef CONFIG_EGA
[1f5c9c96]145 if (!bfb) {
[a71c158]146 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
147 if (egadev)
148 stdout_wire(egadev);
149 }
[ec944b1]150#endif
[a35b458]151
[381465e]152 /* Merge all memory zones to 1 big zone */
153 zone_merge_all();
[babcb148]154 }
155}
156
[36df4109]157void ia32_post_cpu_init(void)
[26678e5]158{
159#ifdef CONFIG_SMP
[49eb681]160 if (config.cpu_active > 1) {
[26678e5]161 l_apic_init();
162 l_apic_debug();
163 }
164#endif
165}
166
[36df4109]167void ia32_pre_smp_init(void)
[babcb148]168{
169 if (config.cpu_active == 1) {
[f619ec11]170#ifdef CONFIG_SMP
[85bfdcc8]171 acpi_init();
[f619ec11]172#endif /* CONFIG_SMP */
[425913b]173 }
[7eade45]174}
175
[36df4109]176void ia32_post_smp_init(void)
[7453929]177{
[eff1f033]178 /* Currently the only supported platform for ia32 is 'pc'. */
179 static const char *platform = "pc";
180
181 sysinfo_set_item_data("platform", NULL, (void *) platform,
182 str_size(platform));
183
[2a34e4c]184#ifdef CONFIG_PC_KBD
[411b6a6]185 /*
[2a34e4c]186 * Initialize the i8042 controller. Then initialize the keyboard
187 * module and connect it to i8042. Enable keyboard interrupts.
[411b6a6]188 */
[c2417bc]189 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
190 if (i8042_instance) {
191 kbrd_instance_t *kbrd_instance = kbrd_init();
192 if (kbrd_instance) {
193 indev_t *sink = stdin_wire();
194 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
195 i8042_wire(i8042_instance, kbrd);
196 trap_virtual_enable_irqs(1 << IRQ_KBD);
[385a3d6]197 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
[c2417bc]198 }
[2a34e4c]199 }
200#endif
[3296df5]201
[6bbe470]202#if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
[3296df5]203 /*
[6bbe470]204 * Initialize the ns16550 controller.
[3296df5]205 */
[21b6307]206#ifdef CONFIG_NS16550_OUT
207 outdev_t *ns16550_out;
208 outdev_t **ns16550_out_ptr = &ns16550_out;
209#else
210 outdev_t **ns16550_out_ptr = NULL;
211#endif
[3bacee1]212 ns16550_instance_t *ns16550_instance =
213 ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
[21b6307]214 ns16550_out_ptr);
[3296df5]215 if (ns16550_instance) {
[6bbe470]216#ifdef CONFIG_NS16550
[3296df5]217 srln_instance_t *srln_instance = srln_init();
218 if (srln_instance) {
219 indev_t *sink = stdin_wire();
220 indev_t *srln = srln_wire(srln_instance, sink);
221 ns16550_wire(ns16550_instance, srln);
[5030acad]222 trap_virtual_enable_irqs(1 << IRQ_NS16550);
[3296df5]223 }
224#endif
[6bbe470]225#ifdef CONFIG_NS16550_OUT
226 if (ns16550_out) {
227 stdout_wire(ns16550_out);
228 }
229#endif
[24b06199]230 }
231#endif
[a35b458]232
[acc7ce4]233 if (irqs_info != NULL)
234 sysinfo_set_item_val(irqs_info, NULL, true);
[7453929]235}
236
[f761f1eb]237void calibrate_delay_loop(void)
238{
239 i8254_calibrate_delay_loop();
[f701b236]240 if (config.cpu_active == 1) {
241 /*
242 * This has to be done only on UP.
243 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
244 */
245 i8254_normal_operation();
246 }
[f761f1eb]247}
[281b607]248
[6da1013f]249/** Construct function pointer
250 *
251 * @param fptr function pointer structure
252 * @param addr function address
253 * @param caller calling function address
254 *
255 * @return address of the function pointer
256 *
257 */
258void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
259{
260 return addr;
261}
262
[149d14e5]263void arch_reboot(void)
264{
265#ifdef CONFIG_PC_KBD
266 i8042_cpu_reset((i8042_t *) I8042_BASE);
267#endif
268}
269
[3a2f8aa]270void irq_initialize_arch(irq_t *irq)
271{
272 (void) irq;
273}
274
[06e1e95]275/** @}
[b45c443]276 */
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