source: mainline/kernel/arch/ia32/src/ia32.c@ 3296df5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3296df5 was 3296df5, checked in by Martin Sucha <sucha14@…>, 13 years ago

Add NS16550 serial input support on ia32 and amd64 platforms.

This is based on ia64 code for the same.
Currently the port used is hardcoded to be COM1.

  • Property mode set to 100644
File size: 6.1 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[deca67b]3 * Copyright (c) 2009 Jiri Svoboda
4 * Copyright (c) 2009 Martin Decky
[f761f1eb]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[06e1e95]31/** @addtogroup ia32
[b45c443]32 * @{
33 */
34/** @file
35 */
36
[f761f1eb]37#include <arch.h>
[d99c1d2]38#include <typedefs.h>
[d8db519]39#include <errno.h>
40#include <memstr.h>
[fcfac420]41#include <interrupt.h>
[41d33ac]42#include <console/console.h>
[d8db519]43#include <syscall/syscall.h>
[4c7257b]44#include <sysinfo/sysinfo.h>
[d8db519]45#include <arch/bios/bios.h>
[deca67b]46#include <arch/boot/boot.h>
[d8db519]47#include <arch/debugger.h>
48#include <arch/drivers/i8254.h>
49#include <arch/drivers/i8259.h>
50#include <genarch/acpi/acpi.h>
51#include <genarch/drivers/ega/ega.h>
52#include <genarch/drivers/i8042/i8042.h>
[3296df5]53#include <genarch/drivers/ns16550/ns16550.h>
[d8db519]54#include <genarch/drivers/legacy/ia32/io.h>
55#include <genarch/fb/bfb.h>
56#include <genarch/kbrd/kbrd.h>
[3296df5]57#include <genarch/srln/srln.h>
[d8db519]58#include <genarch/multiboot/multiboot.h>
59#include <genarch/multiboot/multiboot2.h>
[ad36bd6]60
[26678e5]61#ifdef CONFIG_SMP
62#include <arch/smp/apic.h>
63#endif
64
[5d8d71e]65/** Perform ia32-specific initialization before main_bsp() is called.
[deca67b]66 *
[1f5c9c96]67 * @param signature Multiboot signature.
68 * @param info Multiboot information structure.
69 *
[deca67b]70 */
[1f5c9c96]71void arch_pre_main(uint32_t signature, void *info)
[deca67b]72{
[5d8d71e]73 /* Parse multiboot information obtained from the bootloader. */
[1f5c9c96]74 multiboot_info_parse(signature, (multiboot_info_t *) info);
75 multiboot2_info_parse(signature, (multiboot2_info_t *) info);
[deca67b]76
77#ifdef CONFIG_SMP
78 /* Copy AP bootstrap routines below 1 MB. */
79 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
80 (size_t) &_hardcoded_unmapped_size);
81#endif
82}
83
[f07bba5]84void arch_pre_mm_init(void)
[f761f1eb]85{
86 pm_init();
87
88 if (config.cpu_active == 1) {
[cea12e9]89 interrupt_init();
[dba84ff]90 bios_init();
[5dce48b9]91
[cea12e9]92 /* PIC */
93 i8259_init();
[f761f1eb]94 }
95}
96
[6ba143d]97void arch_post_mm_init(void)
[7eade45]98{
[425913b]99 if (config.cpu_active == 1) {
[cea12e9]100 /* Initialize IRQ routing */
101 irq_init(IRQ_COUNT, IRQ_COUNT);
102
103 /* hard clock */
104 i8254_init();
[ec944b1]105
[a71c158]106#if (defined(CONFIG_FB) || defined(CONFIG_EGA))
[1f5c9c96]107 bool bfb = false;
[a71c158]108#endif
109
[22cf454d]110#ifdef CONFIG_FB
[1f5c9c96]111 bfb = bfb_init();
[22cf454d]112#endif
[a71c158]113
[ec944b1]114#ifdef CONFIG_EGA
[1f5c9c96]115 if (!bfb) {
[a71c158]116 outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
117 if (egadev)
118 stdout_wire(egadev);
119 }
[ec944b1]120#endif
[22cf454d]121
[23d22eb]122 /* Enable debugger */
123 debugger_init();
[381465e]124 /* Merge all memory zones to 1 big zone */
125 zone_merge_all();
[babcb148]126 }
127}
128
[26678e5]129void arch_post_cpu_init()
130{
131#ifdef CONFIG_SMP
[49eb681]132 if (config.cpu_active > 1) {
[26678e5]133 l_apic_init();
134 l_apic_debug();
135 }
136#endif
137}
138
[7453929]139void arch_pre_smp_init(void)
[babcb148]140{
141 if (config.cpu_active == 1) {
[f619ec11]142#ifdef CONFIG_SMP
[85bfdcc8]143 acpi_init();
[f619ec11]144#endif /* CONFIG_SMP */
[425913b]145 }
[7eade45]146}
147
[7453929]148void arch_post_smp_init(void)
149{
[eff1f033]150 /* Currently the only supported platform for ia32 is 'pc'. */
151 static const char *platform = "pc";
152
153 sysinfo_set_item_data("platform", NULL, (void *) platform,
154 str_size(platform));
155
[2a34e4c]156#ifdef CONFIG_PC_KBD
[411b6a6]157 /*
[2a34e4c]158 * Initialize the i8042 controller. Then initialize the keyboard
159 * module and connect it to i8042. Enable keyboard interrupts.
[411b6a6]160 */
[c2417bc]161 i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
162 if (i8042_instance) {
163 kbrd_instance_t *kbrd_instance = kbrd_init();
164 if (kbrd_instance) {
165 indev_t *sink = stdin_wire();
166 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
167 i8042_wire(i8042_instance, kbrd);
168 trap_virtual_enable_irqs(1 << IRQ_KBD);
[385a3d6]169 trap_virtual_enable_irqs(1 << IRQ_MOUSE);
[c2417bc]170 }
[2a34e4c]171 }
172#endif
[3296df5]173
174#ifdef CONFIG_NS16550
175 /*
176 * Initialize the ns16550 controller. Then initialize the serial
177 * input module and connect it to ns16550.
178 */
179 ns16550_instance_t *ns16550_instance
180 = ns16550_init((ns16550_t *) NS16550_BASE, IRQ_NS16550, NULL, NULL);
181 if (ns16550_instance) {
182 srln_instance_t *srln_instance = srln_init();
183 if (srln_instance) {
184 indev_t *sink = stdin_wire();
185 indev_t *srln = srln_wire(srln_instance, sink);
186 ns16550_wire(ns16550_instance, srln);
187 }
188 }
189#endif
[849ed54]190
[acc7ce4]191 if (irqs_info != NULL)
192 sysinfo_set_item_val(irqs_info, NULL, true);
[7453929]193}
194
[f761f1eb]195void calibrate_delay_loop(void)
196{
197 i8254_calibrate_delay_loop();
[f701b236]198 if (config.cpu_active == 1) {
199 /*
200 * This has to be done only on UP.
201 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
202 */
203 i8254_normal_operation();
204 }
[f761f1eb]205}
[281b607]206
[e1be3b6]207/** Set thread-local-storage pointer
[281b607]208 *
[3b712407]209 * TLS pointer is set in GS register. That means, the GS contains
210 * selector, and the descriptor->base is the correct address.
[281b607]211 */
[d8db519]212sysarg_t sys_tls_set(uintptr_t addr)
[281b607]213{
[a6d4ceb]214 THREAD->arch.tls = addr;
[281b607]215 set_tls_desc(addr);
[a71c158]216
[d8db519]217 return EOK;
[281b607]218}
[41d33ac]219
[6da1013f]220/** Construct function pointer
221 *
222 * @param fptr function pointer structure
223 * @param addr function address
224 * @param caller calling function address
225 *
226 * @return address of the function pointer
227 *
228 */
229void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
230{
231 return addr;
232}
233
[149d14e5]234void arch_reboot(void)
235{
236#ifdef CONFIG_PC_KBD
237 i8042_cpu_reset((i8042_t *) I8042_BASE);
238#endif
239}
240
[3a2f8aa]241void irq_initialize_arch(irq_t *irq)
242{
243 (void) irq;
244}
245
[06e1e95]246/** @}
[b45c443]247 */
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