[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[deca67b] | 3 | * Copyright (c) 2009 Jiri Svoboda
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| 4 | * Copyright (c) 2009 Martin Decky
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[f761f1eb] | 5 | * All rights reserved.
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| 6 | *
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| 7 | * Redistribution and use in source and binary forms, with or without
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| 8 | * modification, are permitted provided that the following conditions
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| 9 | * are met:
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| 10 | *
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| 11 | * - Redistributions of source code must retain the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer.
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| 13 | * - Redistributions in binary form must reproduce the above copyright
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| 14 | * notice, this list of conditions and the following disclaimer in the
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| 15 | * documentation and/or other materials provided with the distribution.
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| 16 | * - The name of the author may not be used to endorse or promote products
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| 17 | * derived from this software without specific prior written permission.
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| 18 | *
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 20 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 21 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 22 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 24 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 25 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 26 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 28 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 29 | */
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| 30 |
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[c5429fe] | 31 | /** @addtogroup kernel_ia32
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[b45c443] | 32 | * @{
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| 33 | */
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| 34 | /** @file
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| 35 | */
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| 36 |
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[f761f1eb] | 37 | #include <arch.h>
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[36df4109] | 38 | #include <arch/arch.h>
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[83dab11] | 39 | #include <stdint.h>
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[d8db519] | 40 | #include <errno.h>
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[44a7ee5] | 41 | #include <mem.h>
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[fcfac420] | 42 | #include <interrupt.h>
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[41d33ac] | 43 | #include <console/console.h>
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[d8db519] | 44 | #include <syscall/syscall.h>
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[4c7257b] | 45 | #include <sysinfo/sysinfo.h>
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[d8db519] | 46 | #include <arch/bios/bios.h>
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[deca67b] | 47 | #include <arch/boot/boot.h>
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[d8db519] | 48 | #include <arch/drivers/i8254.h>
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| 49 | #include <genarch/acpi/acpi.h>
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| 50 | #include <genarch/drivers/ega/ega.h>
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| 51 | #include <genarch/drivers/i8042/i8042.h>
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[87a5796] | 52 | #include <genarch/drivers/i8259/i8259.h>
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[3296df5] | 53 | #include <genarch/drivers/ns16550/ns16550.h>
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[d8db519] | 54 | #include <genarch/drivers/legacy/ia32/io.h>
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| 55 | #include <genarch/fb/bfb.h>
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| 56 | #include <genarch/kbrd/kbrd.h>
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[3296df5] | 57 | #include <genarch/srln/srln.h>
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[d8db519] | 58 | #include <genarch/multiboot/multiboot.h>
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| 59 | #include <genarch/multiboot/multiboot2.h>
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[2a103b5] | 60 | #include <genarch/pic/pic_ops.h>
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[d6f9fff] | 61 | #include <arch/pm.h>
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| 62 | #include <arch/vreg.h>
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[ad36bd6] | 63 |
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[26678e5] | 64 | #ifdef CONFIG_SMP
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| 65 | #include <arch/smp/apic.h>
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| 66 | #endif
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| 67 |
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[36df4109] | 68 | static void ia32_pre_mm_init(void);
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| 69 | static void ia32_post_mm_init(void);
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| 70 | static void ia32_post_cpu_init(void);
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| 71 | static void ia32_pre_smp_init(void);
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| 72 | static void ia32_post_smp_init(void);
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| 73 |
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| 74 | arch_ops_t ia32_ops = {
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| 75 | .pre_mm_init = ia32_pre_mm_init,
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| 76 | .post_mm_init = ia32_post_mm_init,
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| 77 | .post_cpu_init = ia32_post_cpu_init,
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| 78 | .pre_smp_init = ia32_pre_smp_init,
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| 79 | .post_smp_init = ia32_post_smp_init,
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| 80 | };
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| 81 |
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| 82 | arch_ops_t *arch_ops = &ia32_ops;
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| 83 |
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[5d8d71e] | 84 | /** Perform ia32-specific initialization before main_bsp() is called.
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[deca67b] | 85 | *
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[1f5c9c96] | 86 | * @param signature Multiboot signature.
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| 87 | * @param info Multiboot information structure.
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| 88 | *
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[deca67b] | 89 | */
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[36df4109] | 90 | void ia32_pre_main(uint32_t signature, void *info)
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[deca67b] | 91 | {
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[5d8d71e] | 92 | /* Parse multiboot information obtained from the bootloader. */
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[1f5c9c96] | 93 | multiboot_info_parse(signature, (multiboot_info_t *) info);
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| 94 | multiboot2_info_parse(signature, (multiboot2_info_t *) info);
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[a35b458] | 95 |
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[deca67b] | 96 | #ifdef CONFIG_SMP
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[bae43dc] | 97 | size_t unmapped_size = (uintptr_t) unmapped_end - BOOT_OFFSET;
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[deca67b] | 98 | /* Copy AP bootstrap routines below 1 MB. */
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[8a1afd2] | 99 | memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET, unmapped_size);
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[deca67b] | 100 | #endif
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| 101 | }
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| 102 |
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[36df4109] | 103 | void ia32_pre_mm_init(void)
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[f761f1eb] | 104 | {
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| 105 | pm_init();
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| 106 |
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| 107 | if (config.cpu_active == 1) {
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[cea12e9] | 108 | interrupt_init();
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[dba84ff] | 109 | bios_init();
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[a35b458] | 110 |
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[cea12e9] | 111 | /* PIC */
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[d1cbad5] | 112 | i8259_init((i8259_t *) I8259_PIC0_BASE,
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[3daba42e] | 113 | (i8259_t *) I8259_PIC1_BASE, IVT_IRQBASE);
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[bbb99f82] | 114 |
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[2a103b5] | 115 | /* Set PIC operations. */
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| 116 | pic_ops = &i8259_pic_ops;
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[f761f1eb] | 117 | }
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| 118 | }
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| 119 |
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[36df4109] | 120 | void ia32_post_mm_init(void)
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[7eade45] | 121 | {
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[d6f9fff] | 122 | vreg_init();
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| 123 |
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[425913b] | 124 | if (config.cpu_active == 1) {
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[cea12e9] | 125 | /* Initialize IRQ routing */
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| 126 | irq_init(IRQ_COUNT, IRQ_COUNT);
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[a35b458] | 127 |
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[cea12e9] | 128 | /* hard clock */
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| 129 | i8254_init();
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[a35b458] | 130 |
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[a71c158] | 131 | #if (defined(CONFIG_FB) || defined(CONFIG_EGA))
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[1f5c9c96] | 132 | bool bfb = false;
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[a71c158] | 133 | #endif
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[a35b458] | 134 |
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[22cf454d] | 135 | #ifdef CONFIG_FB
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[1f5c9c96] | 136 | bfb = bfb_init();
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[22cf454d] | 137 | #endif
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[a35b458] | 138 |
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[ec944b1] | 139 | #ifdef CONFIG_EGA
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[1f5c9c96] | 140 | if (!bfb) {
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[a71c158] | 141 | outdev_t *egadev = ega_init(EGA_BASE, EGA_VIDEORAM);
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| 142 | if (egadev)
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| 143 | stdout_wire(egadev);
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| 144 | }
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[ec944b1] | 145 | #endif
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[a35b458] | 146 |
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[381465e] | 147 | /* Merge all memory zones to 1 big zone */
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| 148 | zone_merge_all();
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[babcb148] | 149 | }
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| 150 | }
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| 151 |
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[36df4109] | 152 | void ia32_post_cpu_init(void)
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[26678e5] | 153 | {
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| 154 | #ifdef CONFIG_SMP
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[49eb681] | 155 | if (config.cpu_active > 1) {
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[26678e5] | 156 | l_apic_init();
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| 157 | l_apic_debug();
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| 158 | }
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| 159 | #endif
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| 160 | }
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| 161 |
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[36df4109] | 162 | void ia32_pre_smp_init(void)
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[babcb148] | 163 | {
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| 164 | if (config.cpu_active == 1) {
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[f619ec11] | 165 | #ifdef CONFIG_SMP
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[85bfdcc8] | 166 | acpi_init();
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[f619ec11] | 167 | #endif /* CONFIG_SMP */
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[425913b] | 168 | }
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[7eade45] | 169 | }
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| 170 |
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[36df4109] | 171 | void ia32_post_smp_init(void)
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[7453929] | 172 | {
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[eff1f033] | 173 | /* Currently the only supported platform for ia32 is 'pc'. */
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| 174 | static const char *platform = "pc";
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| 175 |
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| 176 | sysinfo_set_item_data("platform", NULL, (void *) platform,
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| 177 | str_size(platform));
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| 178 |
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[2a34e4c] | 179 | #ifdef CONFIG_PC_KBD
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[411b6a6] | 180 | /*
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[2a34e4c] | 181 | * Initialize the i8042 controller. Then initialize the keyboard
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| 182 | * module and connect it to i8042. Enable keyboard interrupts.
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[411b6a6] | 183 | */
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[c2417bc] | 184 | i8042_instance_t *i8042_instance = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
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| 185 | if (i8042_instance) {
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| 186 | kbrd_instance_t *kbrd_instance = kbrd_init();
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| 187 | if (kbrd_instance) {
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| 188 | indev_t *sink = stdin_wire();
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| 189 | indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
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| 190 | i8042_wire(i8042_instance, kbrd);
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[2a103b5] | 191 | pic_ops->enable_irqs(1 << IRQ_KBD);
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| 192 | pic_ops->enable_irqs(1 << IRQ_MOUSE);
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[c2417bc] | 193 | }
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[2a34e4c] | 194 | }
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| 195 | #endif
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[3296df5] | 196 |
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[6bbe470] | 197 | #if (defined(CONFIG_NS16550) || defined(CONFIG_NS16550_OUT))
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[3296df5] | 198 | /*
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[6bbe470] | 199 | * Initialize the ns16550 controller.
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[3296df5] | 200 | */
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[21b6307] | 201 | #ifdef CONFIG_NS16550_OUT
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| 202 | outdev_t *ns16550_out;
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| 203 | outdev_t **ns16550_out_ptr = &ns16550_out;
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| 204 | #else
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| 205 | outdev_t **ns16550_out_ptr = NULL;
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| 206 | #endif
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[3bacee1] | 207 | ns16550_instance_t *ns16550_instance =
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| 208 | ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
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[21b6307] | 209 | ns16550_out_ptr);
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[3296df5] | 210 | if (ns16550_instance) {
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[6bbe470] | 211 | #ifdef CONFIG_NS16550
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[3296df5] | 212 | srln_instance_t *srln_instance = srln_init();
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| 213 | if (srln_instance) {
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| 214 | indev_t *sink = stdin_wire();
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| 215 | indev_t *srln = srln_wire(srln_instance, sink);
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| 216 | ns16550_wire(ns16550_instance, srln);
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[2a103b5] | 217 | pic_ops->enable_irqs(1 << IRQ_NS16550);
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[3296df5] | 218 | }
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| 219 | #endif
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[6bbe470] | 220 | #ifdef CONFIG_NS16550_OUT
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| 221 | if (ns16550_out) {
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| 222 | stdout_wire(ns16550_out);
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| 223 | }
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| 224 | #endif
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[24b06199] | 225 | }
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| 226 | #endif
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[a35b458] | 227 |
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[2a103b5] | 228 | sysinfo_set_item_val(pic_ops->get_name(), NULL, true);
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[7453929] | 229 | }
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| 230 |
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[f761f1eb] | 231 | void calibrate_delay_loop(void)
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| 232 | {
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| 233 | i8254_calibrate_delay_loop();
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[f701b236] | 234 | if (config.cpu_active == 1) {
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| 235 | /*
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| 236 | * This has to be done only on UP.
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| 237 | * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
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| 238 | */
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| 239 | i8254_normal_operation();
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| 240 | }
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[f761f1eb] | 241 | }
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[281b607] | 242 |
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[6da1013f] | 243 | /** Construct function pointer
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| 244 | *
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| 245 | * @param fptr function pointer structure
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| 246 | * @param addr function address
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| 247 | * @param caller calling function address
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| 248 | *
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| 249 | * @return address of the function pointer
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| 250 | *
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| 251 | */
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| 252 | void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
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| 253 | {
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| 254 | return addr;
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| 255 | }
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| 256 |
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[149d14e5] | 257 | void arch_reboot(void)
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| 258 | {
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| 259 | #ifdef CONFIG_PC_KBD
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| 260 | i8042_cpu_reset((i8042_t *) I8042_BASE);
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| 261 | #endif
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| 262 | }
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| 263 |
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[3a2f8aa] | 264 | void irq_initialize_arch(irq_t *irq)
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| 265 | {
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| 266 | (void) irq;
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| 267 | }
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| 268 |
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[06e1e95] | 269 | /** @}
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[b45c443] | 270 | */
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