source: mainline/kernel/arch/ia32/src/ia32.c@ 149d14e5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 149d14e5 was 149d14e5, checked in by Martin Decky <martin@…>, 16 years ago

ia32, amd64: do not reboot via a triple fault (which is nasty), but use the i8042 controller to trigger CPU reset

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File size: 5.5 KB
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[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[deca67b]3 * Copyright (c) 2009 Jiri Svoboda
4 * Copyright (c) 2009 Martin Decky
[f761f1eb]5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * - Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * - Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * - The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
[06e1e95]31/** @addtogroup ia32
[b45c443]32 * @{
33 */
34/** @file
35 */
36
[f761f1eb]37#include <arch.h>
38
39#include <arch/types.h>
40
41#include <arch/pm.h>
42
[5d8d71e]43#include <genarch/multiboot/multiboot.h>
[91825d90]44#include <genarch/drivers/legacy/ia32/io.h>
[f245145]45#include <genarch/drivers/ega/ega.h>
[80d31883]46#include <arch/drivers/vesa.h>
[411b6a6]47#include <genarch/drivers/i8042/i8042.h>
48#include <genarch/kbrd/kbrd.h>
[80d31883]49#include <arch/drivers/i8254.h>
50#include <arch/drivers/i8259.h>
[f761f1eb]51
52#include <arch/context.h>
53
54#include <config.h>
55
56#include <arch/interrupt.h>
[ad36bd6]57#include <arch/asm.h>
[e16e036a]58#include <genarch/acpi/acpi.h>
[9c0a9b3]59
60#include <arch/bios/bios.h>
61
[fcfac420]62#include <interrupt.h>
[cea12e9]63#include <ddi/irq.h>
[23d22eb]64#include <arch/debugger.h>
[281b607]65#include <proc/thread.h>
66#include <syscall/syscall.h>
[41d33ac]67#include <console/console.h>
[4c7257b]68#include <sysinfo/sysinfo.h>
[deca67b]69#include <arch/boot/boot.h>
[ad36bd6]70
[26678e5]71#ifdef CONFIG_SMP
72#include <arch/smp/apic.h>
73#endif
74
[5d8d71e]75/** Perform ia32-specific initialization before main_bsp() is called.
[deca67b]76 *
77 * @param signature Should contain the multiboot signature.
78 * @param mi Pointer to the multiboot information structure.
79 */
[5d8d71e]80void arch_pre_main(uint32_t signature, const multiboot_info_t *mi)
[deca67b]81{
[5d8d71e]82 /* Parse multiboot information obtained from the bootloader. */
83 multiboot_info_parse(signature, mi);
[deca67b]84
85#ifdef CONFIG_SMP
86 /* Copy AP bootstrap routines below 1 MB. */
87 memcpy((void *) AP_BOOT_OFFSET, (void *) BOOT_OFFSET,
88 (size_t) &_hardcoded_unmapped_size);
89#endif
90}
91
[f07bba5]92void arch_pre_mm_init(void)
[f761f1eb]93{
94 pm_init();
95
96 if (config.cpu_active == 1) {
[cea12e9]97 interrupt_init();
[dba84ff]98 bios_init();
[5dce48b9]99
[cea12e9]100 /* PIC */
101 i8259_init();
[f761f1eb]102 }
103}
104
[6ba143d]105void arch_post_mm_init(void)
[7eade45]106{
[425913b]107 if (config.cpu_active == 1) {
[cea12e9]108 /* Initialize IRQ routing */
109 irq_init(IRQ_COUNT, IRQ_COUNT);
110
111 /* hard clock */
112 i8254_init();
[ec944b1]113
[22cf454d]114#ifdef CONFIG_FB
[2a34e4c]115 if (vesa_present())
[381465e]116 vesa_init();
[22cf454d]117 else
118#endif
[ec944b1]119#ifdef CONFIG_EGA
120 ega_init(EGA_BASE, EGA_VIDEORAM); /* video */
121#else
122 {}
123#endif
[22cf454d]124
[23d22eb]125 /* Enable debugger */
126 debugger_init();
[381465e]127 /* Merge all memory zones to 1 big zone */
128 zone_merge_all();
[babcb148]129 }
130}
131
[26678e5]132void arch_post_cpu_init()
133{
134#ifdef CONFIG_SMP
135 if (config.cpu_active > 1) {
136 l_apic_init();
137 l_apic_debug();
138 }
139#endif
140}
141
[7453929]142void arch_pre_smp_init(void)
[babcb148]143{
144 if (config.cpu_active == 1) {
[f619ec11]145#ifdef CONFIG_SMP
[85bfdcc8]146 acpi_init();
[f619ec11]147#endif /* CONFIG_SMP */
[425913b]148 }
[7eade45]149}
150
[7453929]151void arch_post_smp_init(void)
152{
[2a34e4c]153#ifdef CONFIG_PC_KBD
[411b6a6]154 /*
[2a34e4c]155 * Initialize the i8042 controller. Then initialize the keyboard
156 * module and connect it to i8042. Enable keyboard interrupts.
[411b6a6]157 */
[84afc7b]158 indev_t *kbrdin = i8042_init((i8042_t *) I8042_BASE, IRQ_KBD);
[2a34e4c]159 if (kbrdin) {
160 kbrd_init(kbrdin);
161 trap_virtual_enable_irqs(1 << IRQ_KBD);
162 }
163
[4c7257b]164 /*
165 * This is the necessary evil until the userspace driver is entirely
166 * self-sufficient.
167 */
168 sysinfo_set_item_val("kbd", NULL, true);
169 sysinfo_set_item_val("kbd.inr", NULL, IRQ_KBD);
[ff685c9]170 sysinfo_set_item_val("kbd.address.physical", NULL,
171 (uintptr_t) I8042_BASE);
172 sysinfo_set_item_val("kbd.address.kernel", NULL,
173 (uintptr_t) I8042_BASE);
[2a34e4c]174#endif
[7453929]175}
176
[f761f1eb]177void calibrate_delay_loop(void)
178{
179 i8254_calibrate_delay_loop();
[f701b236]180 if (config.cpu_active == 1) {
181 /*
182 * This has to be done only on UP.
183 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
184 */
185 i8254_normal_operation();
186 }
[f761f1eb]187}
[281b607]188
[e1be3b6]189/** Set thread-local-storage pointer
[281b607]190 *
[3b712407]191 * TLS pointer is set in GS register. That means, the GS contains
192 * selector, and the descriptor->base is the correct address.
[281b607]193 */
[7f1c620]194unative_t sys_tls_set(unative_t addr)
[281b607]195{
[a6d4ceb]196 THREAD->arch.tls = addr;
[281b607]197 set_tls_desc(addr);
198
199 return 0;
200}
[41d33ac]201
202/** Acquire console back for kernel
203 *
204 */
205void arch_grab_console(void)
206{
[76fca31]207#ifdef CONFIG_FB
[2a34e4c]208 if (vesa_present())
209 vesa_redraw();
210 else
211#endif
212#ifdef CONFIG_EGA
213 ega_redraw();
[76fca31]214#else
[2a34e4c]215 {}
[76fca31]216#endif
[41d33ac]217}
[76fca31]218
[41d33ac]219/** Return console to userspace
220 *
221 */
222void arch_release_console(void)
223{
224}
[b45c443]225
[6da1013f]226/** Construct function pointer
227 *
228 * @param fptr function pointer structure
229 * @param addr function address
230 * @param caller calling function address
231 *
232 * @return address of the function pointer
233 *
234 */
235void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
236{
237 return addr;
238}
239
[149d14e5]240void arch_reboot(void)
241{
242#ifdef CONFIG_PC_KBD
243 i8042_cpu_reset((i8042_t *) I8042_BASE);
244#endif
245}
246
[06e1e95]247/** @}
[b45c443]248 */
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