[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[3c5006a0] | 29 | /** @addtogroup ia32
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[b45c443] | 30 | * @{
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| 31 | */
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[3c5006a0] | 32 | /**
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| 33 | * @file
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| 34 | * @brief PIC driver.
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| 35 | *
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| 36 | * Programmable Interrupt Controller for UP systems based on i8259 chip.
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[b45c443] | 37 | */
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| 38 |
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[80d31883] | 39 | #include <arch/drivers/i8259.h>
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[f761f1eb] | 40 | #include <cpu.h>
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[d99c1d2] | 41 | #include <typedefs.h>
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[f761f1eb] | 42 | #include <arch/asm.h>
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| 43 | #include <arch.h>
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[9c0a9b3] | 44 | #include <print.h>
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[fcfac420] | 45 | #include <interrupt.h>
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[f761f1eb] | 46 |
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[25d7709] | 47 | static void pic_spurious(int n, istate_t *istate);
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[fcfac420] | 48 |
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[f761f1eb] | 49 | void i8259_init(void)
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| 50 | {
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| 51 | /* ICW1: this is ICW1, ICW4 to follow */
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[ee06f2a] | 52 | pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
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[f761f1eb] | 53 |
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| 54 | /* ICW2: IRQ 0 maps to INT IRQBASE */
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[ee06f2a] | 55 | pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
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[76cec1e] | 56 |
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[f761f1eb] | 57 | /* ICW3: pic1 using IRQ IRQ_PIC1 */
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[ee06f2a] | 58 | pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
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[76cec1e] | 59 |
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| 60 | /* ICW4: i8086 mode */
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[ee06f2a] | 61 | pio_write_8(PIC_PIC0PORT2, 1);
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[f761f1eb] | 62 |
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| 63 | /* ICW1: ICW1, ICW4 to follow */
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[ee06f2a] | 64 | pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
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[f761f1eb] | 65 |
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[76cec1e] | 66 | /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
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[ee06f2a] | 67 | pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
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[f761f1eb] | 68 |
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[39ae77b] | 69 | /* ICW3: pic1 is known as IRQ_PIC1 */
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[ee06f2a] | 70 | pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
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[f761f1eb] | 71 |
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[76cec1e] | 72 | /* ICW4: i8086 mode */
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[ee06f2a] | 73 | pio_write_8(PIC_PIC1PORT2, 1);
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[f761f1eb] | 74 |
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| 75 | /*
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| 76 | * Register interrupt handler for the PIC spurious interrupt.
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| 77 | */
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[25d7709] | 78 | exc_register(VECTOR_PIC_SPUR, "pic_spurious", (iroutine) pic_spurious);
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[f761f1eb] | 79 |
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| 80 | /*
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| 81 | * Set the enable/disable IRQs handlers.
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| 82 | * Set the End-of-Interrupt handler.
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| 83 | */
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| 84 | enable_irqs_function = pic_enable_irqs;
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| 85 | disable_irqs_function = pic_disable_irqs;
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| 86 | eoi_function = pic_eoi;
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[76cec1e] | 87 |
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[f761f1eb] | 88 | pic_disable_irqs(0xffff); /* disable all irq's */
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[f619ec11] | 89 | pic_enable_irqs(1 << IRQ_PIC1); /* but enable pic1 */
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[f761f1eb] | 90 | }
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| 91 |
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[7f1c620] | 92 | void pic_enable_irqs(uint16_t irqmask)
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[f761f1eb] | 93 | {
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[7f1c620] | 94 | uint8_t x;
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[76cec1e] | 95 |
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[f761f1eb] | 96 | if (irqmask & 0xff) {
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[ee06f2a] | 97 | x = pio_read_8(PIC_PIC0PORT2);
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| 98 | pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
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[f761f1eb] | 99 | }
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| 100 | if (irqmask >> 8) {
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[ee06f2a] | 101 | x = pio_read_8(PIC_PIC1PORT2);
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| 102 | pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
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[f761f1eb] | 103 | }
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| 104 | }
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| 105 |
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[7f1c620] | 106 | void pic_disable_irqs(uint16_t irqmask)
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[f761f1eb] | 107 | {
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[7f1c620] | 108 | uint8_t x;
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[76cec1e] | 109 |
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[f761f1eb] | 110 | if (irqmask & 0xff) {
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[ee06f2a] | 111 | x = pio_read_8(PIC_PIC0PORT2);
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| 112 | pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
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[f761f1eb] | 113 | }
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| 114 | if (irqmask >> 8) {
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[ee06f2a] | 115 | x = pio_read_8(PIC_PIC1PORT2);
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| 116 | pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
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[f761f1eb] | 117 | }
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| 118 | }
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| 119 |
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| 120 | void pic_eoi(void)
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| 121 | {
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[5cb223f] | 122 | pio_write_8((ioport8_t *)0x20, 0x20);
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| 123 | pio_write_8((ioport8_t *)0xa0, 0x20);
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[f761f1eb] | 124 | }
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| 125 |
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[e8a0b90] | 126 | void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))
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[f761f1eb] | 127 | {
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[14df080] | 128 | #ifdef CONFIG_DEBUG
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[e8a0b90] | 129 | printf("cpu%u: PIC spurious interrupt\n", CPU->id);
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[14df080] | 130 | #endif
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[f761f1eb] | 131 | }
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[b45c443] | 132 |
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[3c5006a0] | 133 | /** @}
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[b45c443] | 134 | */
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