source: mainline/kernel/arch/ia32/src/drivers/i8259.c@ d99c1d2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d99c1d2 was d99c1d2, checked in by Martin Decky <martin@…>, 15 years ago

use [u]int{8|16|32|64}_t type definitions as detected by the autotool
replace direct usage of arch/types.h with typedefs.h

  • Property mode set to 100644
File size: 3.7 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[3c5006a0]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
[3c5006a0]32/**
33 * @file
34 * @brief PIC driver.
35 *
36 * Programmable Interrupt Controller for UP systems based on i8259 chip.
[b45c443]37 */
38
[80d31883]39#include <arch/drivers/i8259.h>
[f761f1eb]40#include <cpu.h>
[d99c1d2]41#include <typedefs.h>
[f761f1eb]42#include <arch/asm.h>
43#include <arch.h>
[9c0a9b3]44#include <print.h>
[fcfac420]45#include <interrupt.h>
[f761f1eb]46
[25d7709]47static void pic_spurious(int n, istate_t *istate);
[fcfac420]48
[f761f1eb]49void i8259_init(void)
50{
51 /* ICW1: this is ICW1, ICW4 to follow */
[ee06f2a]52 pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
[f761f1eb]53
54 /* ICW2: IRQ 0 maps to INT IRQBASE */
[ee06f2a]55 pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE);
[76cec1e]56
[f761f1eb]57 /* ICW3: pic1 using IRQ IRQ_PIC1 */
[ee06f2a]58 pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1);
[76cec1e]59
60 /* ICW4: i8086 mode */
[ee06f2a]61 pio_write_8(PIC_PIC0PORT2, 1);
[f761f1eb]62
63 /* ICW1: ICW1, ICW4 to follow */
[ee06f2a]64 pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
[f761f1eb]65
[76cec1e]66 /* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
[ee06f2a]67 pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8);
[f761f1eb]68
[39ae77b]69 /* ICW3: pic1 is known as IRQ_PIC1 */
[ee06f2a]70 pio_write_8(PIC_PIC1PORT2, IRQ_PIC1);
[f761f1eb]71
[76cec1e]72 /* ICW4: i8086 mode */
[ee06f2a]73 pio_write_8(PIC_PIC1PORT2, 1);
[f761f1eb]74
75 /*
76 * Register interrupt handler for the PIC spurious interrupt.
77 */
[25d7709]78 exc_register(VECTOR_PIC_SPUR, "pic_spurious", (iroutine) pic_spurious);
[f761f1eb]79
80 /*
81 * Set the enable/disable IRQs handlers.
82 * Set the End-of-Interrupt handler.
83 */
84 enable_irqs_function = pic_enable_irqs;
85 disable_irqs_function = pic_disable_irqs;
86 eoi_function = pic_eoi;
[76cec1e]87
[f761f1eb]88 pic_disable_irqs(0xffff); /* disable all irq's */
[f619ec11]89 pic_enable_irqs(1 << IRQ_PIC1); /* but enable pic1 */
[f761f1eb]90}
91
[7f1c620]92void pic_enable_irqs(uint16_t irqmask)
[f761f1eb]93{
[7f1c620]94 uint8_t x;
[76cec1e]95
[f761f1eb]96 if (irqmask & 0xff) {
[ee06f2a]97 x = pio_read_8(PIC_PIC0PORT2);
98 pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff))));
[f761f1eb]99 }
100 if (irqmask >> 8) {
[ee06f2a]101 x = pio_read_8(PIC_PIC1PORT2);
102 pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8))));
[f761f1eb]103 }
104}
105
[7f1c620]106void pic_disable_irqs(uint16_t irqmask)
[f761f1eb]107{
[7f1c620]108 uint8_t x;
[76cec1e]109
[f761f1eb]110 if (irqmask & 0xff) {
[ee06f2a]111 x = pio_read_8(PIC_PIC0PORT2);
112 pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff)));
[f761f1eb]113 }
114 if (irqmask >> 8) {
[ee06f2a]115 x = pio_read_8(PIC_PIC1PORT2);
116 pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8)));
[f761f1eb]117 }
118}
119
120void pic_eoi(void)
121{
[5cb223f]122 pio_write_8((ioport8_t *)0x20, 0x20);
123 pio_write_8((ioport8_t *)0xa0, 0x20);
[f761f1eb]124}
125
[e8a0b90]126void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused)))
[f761f1eb]127{
[14df080]128#ifdef CONFIG_DEBUG
[e8a0b90]129 printf("cpu%u: PIC spurious interrupt\n", CPU->id);
[14df080]130#endif
[f761f1eb]131}
[b45c443]132
[3c5006a0]133/** @}
[b45c443]134 */
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