source: mainline/kernel/arch/ia32/src/cpu/cpu.c@ b3f8fb7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b3f8fb7 was b3f8fb7, checked in by Martin Decky <martin@…>, 19 years ago

huge type system cleanup
remove cyclical type dependencies across multiple header files
many minor coding style fixes

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup ia32
30 * @{
31 */
32/** @file
33 */
34
35#include <arch/cpu.h>
36#include <arch/cpuid.h>
37#include <arch/pm.h>
38
39#include <arch.h>
40#include <arch/types.h>
41#include <print.h>
42#include <fpu_context.h>
43
44#include <arch/smp/apic.h>
45
46/*
47 * Identification of CPUs.
48 * Contains only non-MP-Specification specific SMP code.
49 */
50#define AMD_CPUID_EBX 0x68747541
51#define AMD_CPUID_ECX 0x444d4163
52#define AMD_CPUID_EDX 0x69746e65
53
54#define INTEL_CPUID_EBX 0x756e6547
55#define INTEL_CPUID_ECX 0x6c65746e
56#define INTEL_CPUID_EDX 0x49656e69
57
58
59enum vendor {
60 VendorUnknown=0,
61 VendorAMD,
62 VendorIntel
63};
64
65static char *vendor_str[] = {
66 "Unknown Vendor",
67 "AuthenticAMD",
68 "GenuineIntel"
69};
70
71void fpu_disable(void)
72{
73 asm volatile (
74 "mov %%cr0,%%eax;"
75 "or $8,%%eax;"
76 "mov %%eax,%%cr0;"
77 :
78 :
79 :"%eax"
80 );
81}
82
83void fpu_enable(void)
84{
85 asm volatile (
86 "mov %%cr0,%%eax;"
87 "and $0xffFFffF7,%%eax;"
88 "mov %%eax,%%cr0;"
89 :
90 :
91 :"%eax"
92 );
93}
94
95void cpu_arch_init(void)
96{
97 cpuid_feature_info fi;
98 cpuid_extended_feature_info efi;
99 cpu_info_t info;
100 uint32_t help = 0;
101
102 CPU->arch.tss = tss_p;
103 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
104
105 CPU->fpu_owner = NULL;
106
107 cpuid(1, &info);
108
109 fi.word = info.cpuid_edx;
110 efi.word = info.cpuid_ecx;
111
112 if (fi.bits.fxsr)
113 fpu_fxsr();
114 else
115 fpu_fsr();
116
117 if (fi.bits.sse) {
118 asm volatile (
119 "mov %%cr4,%0\n"
120 "or %1,%0\n"
121 "mov %0,%%cr4\n"
122 : "+r" (help)
123 : "i" (CR4_OSFXSR_MASK|(1<<10))
124 );
125 }
126}
127
128void cpu_identify(void)
129{
130 cpu_info_t info;
131
132 CPU->arch.vendor = VendorUnknown;
133 if (has_cpuid()) {
134 cpuid(0, &info);
135
136 /*
137 * Check for AMD processor.
138 */
139 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
140 CPU->arch.vendor = VendorAMD;
141 }
142
143 /*
144 * Check for Intel processor.
145 */
146 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
147 CPU->arch.vendor = VendorIntel;
148 }
149
150 cpuid(1, &info);
151 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
152 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
153 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
154 }
155}
156
157void cpu_print_report(cpu_t* m)
158{
159 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
160 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
161 m->frequency_mhz);
162}
163
164/** @}
165 */
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