source: mainline/kernel/arch/ia32/src/cpu/cpu.c@ 33eb919

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 33eb919 was 33eb919, checked in by Jakub Jermar <jakub@…>, 16 years ago

Use defined macros instead of magic constants.

  • Property mode set to 100644
File size: 4.0 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[1bb2e7a]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[f761f1eb]35#include <arch/cpu.h>
36#include <arch/cpuid.h>
37#include <arch/pm.h>
38
39#include <arch.h>
40#include <arch/types.h>
41#include <print.h>
[1084a784]42#include <fpu_context.h>
[f761f1eb]43
[8262010]44#include <arch/smp/apic.h>
[f2ef7fd]45#include <arch/syscall.h>
[8262010]46
[f761f1eb]47/*
48 * Identification of CPUs.
49 * Contains only non-MP-Specification specific SMP code.
50 */
[add04f7]51#define AMD_CPUID_EBX 0x68747541
52#define AMD_CPUID_ECX 0x444d4163
53#define AMD_CPUID_EDX 0x69746e65
[f761f1eb]54
[add04f7]55#define INTEL_CPUID_EBX 0x756e6547
56#define INTEL_CPUID_ECX 0x6c65746e
57#define INTEL_CPUID_EDX 0x49656e69
[f761f1eb]58
[c192134]59
[f761f1eb]60enum vendor {
[add04f7]61 VendorUnknown = 0,
[f761f1eb]62 VendorAMD,
63 VendorIntel
64};
65
66static char *vendor_str[] = {
67 "Unknown Vendor",
[76fca31]68 "AMD",
69 "Intel"
[f761f1eb]70};
71
[b49f4ae]72void fpu_disable(void)
[79f1f38f]73{
[e7b7be3f]74 asm volatile (
[add04f7]75 "mov %%cr0, %%eax\n"
76 "or $8, %%eax\n"
77 "mov %%eax, %%cr0\n"
78 ::: "%eax"
[79f1f38f]79 );
80}
81
[b49f4ae]82void fpu_enable(void)
[79f1f38f]83{
[e7b7be3f]84 asm volatile (
[add04f7]85 "mov %%cr0, %%eax\n"
86 "and $0xffFFffF7, %%eax\n"
87 "mov %%eax,%%cr0\n"
88 ::: "%eax"
89 );
[79f1f38f]90}
91
[f761f1eb]92void cpu_arch_init(void)
93{
[39cea6a]94 cpuid_feature_info fi;
95 cpuid_extended_feature_info efi;
96 cpu_info_t info;
[7f1c620]97 uint32_t help = 0;
[3b05862f]98
[43114c5]99 CPU->arch.tss = tss_p;
[7f1c620]100 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((uint8_t *) CPU->arch.tss);
[add04f7]101
[39cea6a]102 CPU->fpu_owner = NULL;
[add04f7]103
[33eb919]104 cpuid(INTEL_CPUID_STANDARD, &info);
[add04f7]105
[39cea6a]106 fi.word = info.cpuid_edx;
107 efi.word = info.cpuid_ecx;
[3b05862f]108
[39cea6a]109 if (fi.bits.fxsr)
110 fpu_fxsr();
111 else
[add04f7]112 fpu_fsr();
[3b05862f]113
[39cea6a]114 if (fi.bits.sse) {
115 asm volatile (
[add04f7]116 "mov %%cr4, %[help]\n"
117 "or %[mask], %[help]\n"
118 "mov %[help], %%cr4\n"
119 : [help] "+r" (help)
120 : [mask] "i" (CR4_OSFXSR_MASK | (1 << 10))
[39cea6a]121 );
122 }
[f2ef7fd]123
124 /* Setup fast SYSENTER/SYSEXIT syscalls */
125 syscall_setup_cpu();
[f761f1eb]126}
127
128void cpu_identify(void)
129{
130 cpu_info_t info;
131
[43114c5]132 CPU->arch.vendor = VendorUnknown;
[f761f1eb]133 if (has_cpuid()) {
[33eb919]134 cpuid(INTEL_CPUID_LEVEL, &info);
[f761f1eb]135
136 /*
137 * Check for AMD processor.
138 */
[76fca31]139 if ((info.cpuid_ebx == AMD_CPUID_EBX)
140 && (info.cpuid_ecx == AMD_CPUID_ECX)
141 && (info.cpuid_edx == AMD_CPUID_EDX))
[43114c5]142 CPU->arch.vendor = VendorAMD;
[76fca31]143
[f761f1eb]144 /*
145 * Check for Intel processor.
146 */
[76fca31]147 if ((info.cpuid_ebx == INTEL_CPUID_EBX)
148 && (info.cpuid_ecx == INTEL_CPUID_ECX)
149 && (info.cpuid_edx == INTEL_CPUID_EDX))
[43114c5]150 CPU->arch.vendor = VendorIntel;
[76fca31]151
[33eb919]152 cpuid(INTEL_CPUID_STANDARD, &info);
[76fca31]153 CPU->arch.family = (info.cpuid_eax >> 8) & 0x0f;
154 CPU->arch.model = (info.cpuid_eax >> 4) & 0x0f;
155 CPU->arch.stepping = (info.cpuid_eax >> 0) & 0x0f;
[f761f1eb]156 }
157}
158
[76fca31]159void cpu_print_report(cpu_t* cpu)
[f761f1eb]160{
[76fca31]161 printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
162 cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
163 cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
[f761f1eb]164}
[b45c443]165
[1bb2e7a]166/** @}
[b45c443]167 */
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