source: mainline/kernel/arch/ia32/include/smp/apic.h@ 2c4fb51

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2c4fb51 was f4c2b6a, checked in by Martin Decky <martin@…>, 17 years ago

reflect changes in generic code
proper formatting directives
coding style
  • Property mode set to 100644
File size: 9.8 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia32
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ia32_APIC_H_
36#define KERN_ia32_APIC_H_
[f761f1eb]37
38#include <arch/types.h>
39#include <cpu.h>
40
41#define FIXED (0<<0)
42#define LOPRI (1<<0)
43
[9149135]44#define APIC_ID_COUNT 16
45
[f761f1eb]46/* local APIC macros */
47#define IPI_INIT 0
48#define IPI_STARTUP 0
49
[8418c7d]50/** Delivery modes. */
51#define DELMOD_FIXED 0x0
52#define DELMOD_LOWPRI 0x1
53#define DELMOD_SMI 0x2
54/* 0x3 reserved */
55#define DELMOD_NMI 0x4
56#define DELMOD_INIT 0x5
57#define DELMOD_STARTUP 0x6
58#define DELMOD_EXTINT 0x7
59
60/** Destination modes. */
61#define DESTMOD_PHYS 0x0
62#define DESTMOD_LOGIC 0x1
63
64/** Trigger Modes. */
65#define TRIGMOD_EDGE 0x0
66#define TRIGMOD_LEVEL 0x1
67
68/** Levels. */
69#define LEVEL_DEASSERT 0x0
70#define LEVEL_ASSERT 0x1
71
72/** Destination Shorthands. */
73#define SHORTHAND_NONE 0x0
74#define SHORTHAND_SELF 0x1
75#define SHORTHAND_ALL_INCL 0x2
76#define SHORTHAND_ALL_EXCL 0x3
77
78/** Interrupt Input Pin Polarities. */
79#define POLARITY_HIGH 0x0
80#define POLARITY_LOW 0x1
[f761f1eb]81
[f701b236]82/** Divide Values. (Bit 2 is always 0) */
83#define DIVIDE_2 0x0
84#define DIVIDE_4 0x1
85#define DIVIDE_8 0x2
86#define DIVIDE_16 0x3
87#define DIVIDE_32 0x8
88#define DIVIDE_64 0x9
89#define DIVIDE_128 0xa
90#define DIVIDE_1 0xb
91
92/** Timer Modes. */
93#define TIMER_ONESHOT 0x0
94#define TIMER_PERIODIC 0x1
95
[9149135]96/** Delivery status. */
97#define DELIVS_IDLE 0x0
98#define DELIVS_PENDING 0x1
99
100/** Destination masks. */
101#define DEST_ALL 0xff
[f761f1eb]102
[93e90c7]103/** Dest format models. */
104#define MODEL_FLAT 0xf
105#define MODEL_CLUSTER 0x0
106
[8418c7d]107/** Interrupt Command Register. */
[f4c2b6a]108#define ICRlo (0x300 / sizeof(uint32_t))
109#define ICRhi (0x310 / sizeof(uint32_t))
[b3f8fb7]110typedef struct {
[8418c7d]111 union {
[7f1c620]112 uint32_t lo;
[8418c7d]113 struct {
[7f1c620]114 uint8_t vector; /**< Interrupt Vector. */
[8418c7d]115 unsigned delmod : 3; /**< Delivery Mode. */
116 unsigned destmod : 1; /**< Destination Mode. */
117 unsigned delivs : 1; /**< Delivery status (RO). */
118 unsigned : 1; /**< Reserved. */
119 unsigned level : 1; /**< Level. */
120 unsigned trigger_mode : 1; /**< Trigger Mode. */
121 unsigned : 2; /**< Reserved. */
122 unsigned shorthand : 2; /**< Destination Shorthand. */
123 unsigned : 12; /**< Reserved. */
124 } __attribute__ ((packed));
125 };
126 union {
[7f1c620]127 uint32_t hi;
[8418c7d]128 struct {
129 unsigned : 24; /**< Reserved. */
[7f1c620]130 uint8_t dest; /**< Destination field. */
[8418c7d]131 } __attribute__ ((packed));
132 };
[b3f8fb7]133} __attribute__ ((packed)) icr_t;
[f761f1eb]134
[11928d5]135/* End Of Interrupt. */
[f4c2b6a]136#define EOI (0x0b0 / sizeof(uint32_t))
[f761f1eb]137
[f701b236]138/** Error Status Register. */
[f4c2b6a]139#define ESR (0x280 / sizeof(uint32_t))
[b3f8fb7]140typedef union {
[7f1c620]141 uint32_t value;
142 uint8_t err_bitmap;
[f701b236]143 struct {
144 unsigned send_checksum_error : 1;
145 unsigned receive_checksum_error : 1;
146 unsigned send_accept_error : 1;
147 unsigned receive_accept_error : 1;
148 unsigned : 1;
149 unsigned send_illegal_vector : 1;
150 unsigned received_illegal_vector : 1;
151 unsigned illegal_register_address : 1;
152 unsigned : 24;
153 } __attribute__ ((packed));
[b3f8fb7]154} esr_t;
[f761f1eb]155
156/* Task Priority Register */
[f4c2b6a]157#define TPR (0x080 / sizeof(uint32_t))
[b3f8fb7]158typedef union {
[7f1c620]159 uint32_t value;
[d0780b4c]160 struct {
161 unsigned pri_sc : 4; /**< Task Priority Sub-Class. */
162 unsigned pri : 4; /**< Task Priority. */
163 } __attribute__ ((packed));
[b3f8fb7]164} tpr_t;
[f761f1eb]165
[8418c7d]166/** Spurious-Interrupt Vector Register. */
[f4c2b6a]167#define SVR (0x0f0 / sizeof(uint32_t))
[b3f8fb7]168typedef union {
[7f1c620]169 uint32_t value;
[8418c7d]170 struct {
[7f1c620]171 uint8_t vector; /**< Spurious Vector. */
[d0780b4c]172 unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
173 unsigned focus_checking : 1; /**< Focus Processor Checking. */
[8418c7d]174 unsigned : 22; /**< Reserved. */
175 } __attribute__ ((packed));
[b3f8fb7]176} svr_t;
[f761f1eb]177
[f701b236]178/** Time Divide Configuration Register. */
[f4c2b6a]179#define TDCR (0x3e0 / sizeof(uint32_t))
[b3f8fb7]180typedef union {
[7f1c620]181 uint32_t value;
[f701b236]182 struct {
183 unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */
184 unsigned : 28; /**< Reserved. */
185 } __attribute__ ((packed));
[b3f8fb7]186} tdcr_t;
[f761f1eb]187
188/* Initial Count Register for Timer */
[f4c2b6a]189#define ICRT (0x380 / sizeof(uint32_t))
[f761f1eb]190
191/* Current Count Register for Timer */
[f4c2b6a]192#define CCRT (0x390 / sizeof(uint32_t))
[f761f1eb]193
[8418c7d]194/** LVT Timer register. */
[f4c2b6a]195#define LVT_Tm (0x320 / sizeof(uint32_t))
[b3f8fb7]196typedef union {
[7f1c620]197 uint32_t value;
[8418c7d]198 struct {
[7f1c620]199 uint8_t vector; /**< Local Timer Interrupt vector. */
[8418c7d]200 unsigned : 4; /**< Reserved. */
201 unsigned delivs : 1; /**< Delivery status (RO). */
202 unsigned : 3; /**< Reserved. */
203 unsigned masked : 1; /**< Interrupt Mask. */
204 unsigned mode : 1; /**< Timer Mode. */
205 unsigned : 14; /**< Reserved. */
206 } __attribute__ ((packed));
[b3f8fb7]207} lvt_tm_t;
[8418c7d]208
209/** LVT LINT registers. */
[f4c2b6a]210#define LVT_LINT0 (0x350 / sizeof(uint32_t))
211#define LVT_LINT1 (0x360 / sizeof(uint32_t))
[b3f8fb7]212typedef union {
[7f1c620]213 uint32_t value;
[8418c7d]214 struct {
[7f1c620]215 uint8_t vector; /**< LINT Interrupt vector. */
[8418c7d]216 unsigned delmod : 3; /**< Delivery Mode. */
217 unsigned : 1; /**< Reserved. */
218 unsigned delivs : 1; /**< Delivery status (RO). */
219 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
220 unsigned irr : 1; /**< Remote IRR (RO). */
221 unsigned trigger_mode : 1; /**< Trigger Mode. */
222 unsigned masked : 1; /**< Interrupt Mask. */
223 unsigned : 15; /**< Reserved. */
224 } __attribute__ ((packed));
[b3f8fb7]225} lvt_lint_t;
[8418c7d]226
227/** LVT Error register. */
[f4c2b6a]228#define LVT_Err (0x370 / sizeof(uint32_t))
[b3f8fb7]229typedef union {
[7f1c620]230 uint32_t value;
[8418c7d]231 struct {
[7f1c620]232 uint8_t vector; /**< Local Timer Interrupt vector. */
[8418c7d]233 unsigned : 4; /**< Reserved. */
234 unsigned delivs : 1; /**< Delivery status (RO). */
235 unsigned : 3; /**< Reserved. */
236 unsigned masked : 1; /**< Interrupt Mask. */
237 unsigned : 15; /**< Reserved. */
238 } __attribute__ ((packed));
[b3f8fb7]239} lvt_error_t;
[8418c7d]240
[f701b236]241/** Local APIC ID Register. */
[f4c2b6a]242#define L_APIC_ID (0x020 / sizeof(uint32_t))
[b3f8fb7]243typedef union {
[7f1c620]244 uint32_t value;
[f701b236]245 struct {
246 unsigned : 24; /**< Reserved. */
[7f1c620]247 uint8_t apic_id; /**< Local APIC ID. */
[f701b236]248 } __attribute__ ((packed));
[b3f8fb7]249} l_apic_id_t;
[f761f1eb]250
[11928d5]251/** Local APIC Version Register */
[f4c2b6a]252#define LAVR (0x030 / sizeof(uint32_t))
[c9b8c5c]253#define LAVR_Mask 0xff
[f4c2b6a]254#define is_local_apic(x) (((x) & LAVR_Mask & 0xf0) == 0x1)
255#define is_82489DX_apic(x) ((((x) & LAVR_Mask & 0xf0) == 0x0))
256#define is_local_xapic(x) (((x) & LAVR_Mask) == 0x14)
[c9b8c5c]257
[93e90c7]258/** Logical Destination Register. */
[f4c2b6a]259#define LDR (0x0d0 / sizeof(uint32_t))
[b3f8fb7]260typedef union {
[7f1c620]261 uint32_t value;
[93e90c7]262 struct {
[11928d5]263 unsigned : 24; /**< Reserved. */
[7f1c620]264 uint8_t id; /**< Logical APIC ID. */
[93e90c7]265 } __attribute__ ((packed));
[b3f8fb7]266} ldr_t;
[93e90c7]267
268/** Destination Format Register. */
[f4c2b6a]269#define DFR (0x0e0 / sizeof(uint32_t))
[b3f8fb7]270typedef union {
[7f1c620]271 uint32_t value;
[93e90c7]272 struct {
273 unsigned : 28; /**< Reserved, all ones. */
274 unsigned model : 4; /**< Model. */
275 } __attribute__ ((packed));
[b3f8fb7]276} dfr_t;
[93e90c7]277
[f761f1eb]278/* IO APIC */
[f4c2b6a]279#define IOREGSEL (0x00 / sizeof(uint32_t))
280#define IOWIN (0x10 / sizeof(uint32_t))
[f761f1eb]281
282#define IOAPICID 0x00
283#define IOAPICVER 0x01
284#define IOAPICARB 0x02
285#define IOREDTBL 0x10
286
[f701b236]287/** I/O Register Select Register. */
[b3f8fb7]288typedef union {
[7f1c620]289 uint32_t value;
[f701b236]290 struct {
[7f1c620]291 uint8_t reg_addr; /**< APIC Register Address. */
[f701b236]292 unsigned : 24; /**< Reserved. */
293 } __attribute__ ((packed));
[b3f8fb7]294} io_regsel_t;
[f701b236]295
[a83a802]296/** I/O Redirection Register. */
[b3f8fb7]297typedef struct io_redirection_reg {
[a83a802]298 union {
[7f1c620]299 uint32_t lo;
[a83a802]300 struct {
[7f1c620]301 uint8_t intvec; /**< Interrupt Vector. */
[a83a802]302 unsigned delmod : 3; /**< Delivery Mode. */
303 unsigned destmod : 1; /**< Destination mode. */
304 unsigned delivs : 1; /**< Delivery status (RO). */
305 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
306 unsigned irr : 1; /**< Remote IRR (RO). */
307 unsigned trigger_mode : 1; /**< Trigger Mode. */
308 unsigned masked : 1; /**< Interrupt Mask. */
309 unsigned : 15; /**< Reserved. */
[8418c7d]310 } __attribute__ ((packed));
[a83a802]311 };
312 union {
[7f1c620]313 uint32_t hi;
[a83a802]314 struct {
315 unsigned : 24; /**< Reserved. */
[7f1c620]316 uint8_t dest : 8; /**< Destination Field. */
[8418c7d]317 } __attribute__ ((packed));
[a83a802]318 };
319
[b3f8fb7]320} __attribute__ ((packed)) io_redirection_reg_t;
[f761f1eb]321
[9149135]322
323/** IO APIC Identification Register. */
[b3f8fb7]324typedef union {
[7f1c620]325 uint32_t value;
[9149135]326 struct {
327 unsigned : 24; /**< Reserved. */
328 unsigned apic_id : 4; /**< IO APIC ID. */
329 unsigned : 4; /**< Reserved. */
330 } __attribute__ ((packed));
[b3f8fb7]331} io_apic_id_t;
[9149135]332
[7f1c620]333extern volatile uint32_t *l_apic;
334extern volatile uint32_t *io_apic;
[f761f1eb]335
[7f1c620]336extern uint32_t apic_id_mask;
[f761f1eb]337
338extern void apic_init(void);
339
340extern void l_apic_init(void);
341extern void l_apic_eoi(void);
[7f1c620]342extern int l_apic_broadcast_custom_ipi(uint8_t vector);
343extern int l_apic_send_init_ipi(uint8_t apicid);
[f761f1eb]344extern void l_apic_debug(void);
[7f1c620]345extern uint8_t l_apic_id(void);
[f761f1eb]346
[7f1c620]347extern uint32_t io_apic_read(uint8_t address);
348extern void io_apic_write(uint8_t address , uint32_t x);
[7f043c0]349extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);
[7f1c620]350extern void io_apic_disable_irqs(uint16_t irqmask);
351extern void io_apic_enable_irqs(uint16_t irqmask);
[f761f1eb]352
353#endif
[b45c443]354
[06e1e95]355/** @}
[b45c443]356 */
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