[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[06e1e95] | 29 | /** @addtogroup ia32mm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | */
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| 34 |
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[06e1e95] | 35 | #ifndef KERN_ia32_PAGE_H_
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| 36 | #define KERN_ia32_PAGE_H_
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[f761f1eb] | 37 |
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[d1f8a87] | 38 | #include <arch/mm/frame.h>
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| 39 |
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[086d4fd] | 40 | #define PAGE_WIDTH FRAME_WIDTH
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[f761f1eb] | 41 | #define PAGE_SIZE FRAME_SIZE
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| 42 |
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[d0485c6] | 43 | #define PAGE_COLOR_BITS 0 /* dummy */
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| 44 |
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[d1f8a87] | 45 | #ifdef KERNEL
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| 46 |
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[8f2153b] | 47 | #ifndef __ASM__
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[7f1c620] | 48 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
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| 49 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
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[8f2153b] | 50 | #else
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[45d6add] | 51 | # define KA2PA(x) ((x) - 0x80000000)
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| 52 | # define PA2KA(x) ((x) + 0x80000000)
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[8f2153b] | 53 | #endif
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[f761f1eb] | 54 |
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[992bbb97] | 55 | /*
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| 56 | * Implementation of generic 4-level page table interface.
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| 57 | * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
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| 58 | */
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[c03ee1c] | 59 |
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| 60 | /* Number of entries in each level. */
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[ecbdc724] | 61 | #define PTL0_ENTRIES_ARCH 1024
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| 62 | #define PTL1_ENTRIES_ARCH 0
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| 63 | #define PTL2_ENTRIES_ARCH 0
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| 64 | #define PTL3_ENTRIES_ARCH 1024
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| 65 |
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[c03ee1c] | 66 | /* Page table sizes for each level. */
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| 67 | #define PTL0_SIZE_ARCH ONE_FRAME
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| 68 | #define PTL1_SIZE_ARCH 0
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| 69 | #define PTL2_SIZE_ARCH 0
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| 70 | #define PTL3_SIZE_ARCH ONE_FRAME
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[6b781c0] | 71 |
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[c03ee1c] | 72 | /* Macros calculating indices for each level. */
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[b3f8fb7] | 73 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
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[992bbb97] | 74 | #define PTL1_INDEX_ARCH(vaddr) 0
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| 75 | #define PTL2_INDEX_ARCH(vaddr) 0
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[b3f8fb7] | 76 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
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[992bbb97] | 77 |
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[c03ee1c] | 78 | /* Get PTE address accessors for each level. */
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| 79 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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| 80 | ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12))
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| 81 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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| 82 | (ptl1)
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| 83 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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| 84 | (ptl2)
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| 85 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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| 86 | ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12))
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| 87 |
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| 88 | /* Set PTE address accessors for each level. */
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| 89 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \
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| 90 | (write_cr3((uintptr_t) (ptl0)))
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| 91 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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| 92 | (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12)
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[ff9f858] | 93 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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| 94 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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[c03ee1c] | 95 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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| 96 | (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12)
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| 97 |
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| 98 | /* Get PTE flags accessors for each level. */
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| 99 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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| 100 | get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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| 101 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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| 102 | PAGE_PRESENT
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| 103 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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| 104 | PAGE_PRESENT
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| 105 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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| 106 | get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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| 107 |
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| 108 | /* Set PTE flags accessors for each level. */
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| 109 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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| 110 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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[ff9f858] | 111 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
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| 112 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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[c03ee1c] | 113 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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| 114 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
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| 115 |
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| 116 | /* Macros for querying the last level entries. */
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| 117 | #define PTE_VALID_ARCH(p) \
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| 118 | (*((uint32_t *) (p)) != 0)
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| 119 | #define PTE_PRESENT_ARCH(p) \
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| 120 | ((p)->present != 0)
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| 121 | #define PTE_GET_FRAME_ARCH(p) \
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| 122 | ((p)->frame_address << FRAME_WIDTH)
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| 123 | #define PTE_WRITABLE_ARCH(p) \
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| 124 | ((p)->writeable != 0)
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[fb84455] | 125 | #define PTE_EXECUTABLE_ARCH(p) 1
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[ecbdc724] | 126 |
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[8f2153b] | 127 | #ifndef __ASM__
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| 128 |
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[b3f8fb7] | 129 | #include <mm/mm.h>
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| 130 | #include <arch/interrupt.h>
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[8f2153b] | 131 |
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[567807b1] | 132 | /* Page fault error codes. */
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| 133 |
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[c03ee1c] | 134 | /** When bit on this position is 0, the page fault was caused by a not-present
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| 135 | * page.
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| 136 | */
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[b3f8fb7] | 137 | #define PFERR_CODE_P (1 << 0)
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[567807b1] | 138 |
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| 139 | /** When bit on this position is 1, the page fault was caused by a write. */
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[b3f8fb7] | 140 | #define PFERR_CODE_RW (1 << 1)
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[567807b1] | 141 |
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| 142 | /** When bit on this position is 1, the page fault was caused in user mode. */
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[b3f8fb7] | 143 | #define PFERR_CODE_US (1 << 2)
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[567807b1] | 144 |
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| 145 | /** When bit on this position is 1, a reserved bit was set in page directory. */
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[b3f8fb7] | 146 | #define PFERR_CODE_RSVD (1 << 3)
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[f761f1eb] | 147 |
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[ff9f858] | 148 | static inline int get_pt_flags(pte_t *pt, index_t i)
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| 149 | {
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| 150 | pte_t *p = &pt[i];
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| 151 |
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[c03ee1c] | 152 | return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
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| 153 | (!p->present) << PAGE_PRESENT_SHIFT |
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| 154 | p->uaccessible << PAGE_USER_SHIFT |
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| 155 | 1 << PAGE_READ_SHIFT |
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| 156 | p->writeable << PAGE_WRITE_SHIFT |
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| 157 | 1 << PAGE_EXEC_SHIFT |
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| 158 | p->global << PAGE_GLOBAL_SHIFT);
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[ff9f858] | 159 | }
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| 160 |
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| 161 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
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| 162 | {
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| 163 | pte_t *p = &pt[i];
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| 164 |
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| 165 | p->page_cache_disable = !(flags & PAGE_CACHEABLE);
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| 166 | p->present = !(flags & PAGE_NOT_PRESENT);
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[51029384] | 167 | p->uaccessible = (flags & PAGE_USER) != 0;
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| 168 | p->writeable = (flags & PAGE_WRITE) != 0;
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[bfb87df] | 169 | p->global = (flags & PAGE_GLOBAL) != 0;
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[0882a9a] | 170 |
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| 171 | /*
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[c03ee1c] | 172 | * Ensure that there is at least one bit set even if the present bit is
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| 173 | * cleared.
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[0882a9a] | 174 | */
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| 175 | p->soft_valid = true;
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[ff9f858] | 176 | }
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[992bbb97] | 177 |
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[f761f1eb] | 178 | extern void page_arch_init(void);
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[567807b1] | 179 | extern void page_fault(int n, istate_t *istate);
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[f761f1eb] | 180 |
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[8f2153b] | 181 | #endif /* __ASM__ */
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| 182 |
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[d1f8a87] | 183 | #endif /* KERNEL */
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| 184 |
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[f761f1eb] | 185 | #endif
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[b45c443] | 186 |
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[06e1e95] | 187 | /** @}
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[b45c443] | 188 | */
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