source: mainline/kernel/arch/ia32/include/mm/page.h@ 0b5f9fa

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 0b5f9fa was c03ee1c, checked in by Jakub Jermar <jakub@…>, 18 years ago

Improve comments for arch-specific implementations of hierarchical
4-level page tables. Improve formatting.

  • Property mode set to 100644
File size: 5.7 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[06e1e95]29/** @addtogroup ia32mm
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ia32_PAGE_H_
36#define KERN_ia32_PAGE_H_
[f761f1eb]37
[d1f8a87]38#include <arch/mm/frame.h>
39
[086d4fd]40#define PAGE_WIDTH FRAME_WIDTH
[f761f1eb]41#define PAGE_SIZE FRAME_SIZE
42
[d0485c6]43#define PAGE_COLOR_BITS 0 /* dummy */
44
[d1f8a87]45#ifdef KERNEL
46
[8f2153b]47#ifndef __ASM__
[7f1c620]48# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
49# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
[8f2153b]50#else
[45d6add]51# define KA2PA(x) ((x) - 0x80000000)
52# define PA2KA(x) ((x) + 0x80000000)
[8f2153b]53#endif
[f761f1eb]54
[992bbb97]55/*
56 * Implementation of generic 4-level page table interface.
57 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
58 */
[c03ee1c]59
60/* Number of entries in each level. */
[ecbdc724]61#define PTL0_ENTRIES_ARCH 1024
62#define PTL1_ENTRIES_ARCH 0
63#define PTL2_ENTRIES_ARCH 0
64#define PTL3_ENTRIES_ARCH 1024
65
[c03ee1c]66/* Page table sizes for each level. */
67#define PTL0_SIZE_ARCH ONE_FRAME
68#define PTL1_SIZE_ARCH 0
69#define PTL2_SIZE_ARCH 0
70#define PTL3_SIZE_ARCH ONE_FRAME
[6b781c0]71
[c03ee1c]72/* Macros calculating indices for each level. */
[b3f8fb7]73#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
[992bbb97]74#define PTL1_INDEX_ARCH(vaddr) 0
75#define PTL2_INDEX_ARCH(vaddr) 0
[b3f8fb7]76#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
[992bbb97]77
[c03ee1c]78/* Get PTE address accessors for each level. */
79#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
80 ((pte_t *) ((((pte_t *) (ptl0))[(i)].frame_address) << 12))
81#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
82 (ptl1)
83#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
84 (ptl2)
85#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
86 ((uintptr_t) ((((pte_t *) (ptl3))[(i)].frame_address) << 12))
87
88/* Set PTE address accessors for each level. */
89#define SET_PTL0_ADDRESS_ARCH(ptl0) \
90 (write_cr3((uintptr_t) (ptl0)))
91#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
92 (((pte_t *) (ptl0))[(i)].frame_address = (a) >> 12)
[ff9f858]93#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
94#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
[c03ee1c]95#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
96 (((pte_t *) (ptl3))[(i)].frame_address = (a) >> 12)
97
98/* Get PTE flags accessors for each level. */
99#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
100 get_pt_flags((pte_t *) (ptl0), (index_t) (i))
101#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
102 PAGE_PRESENT
103#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
104 PAGE_PRESENT
105#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
106 get_pt_flags((pte_t *) (ptl3), (index_t) (i))
107
108/* Set PTE flags accessors for each level. */
109#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
110 set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
[ff9f858]111#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
112#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
[c03ee1c]113#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
114 set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
115
116/* Macros for querying the last level entries. */
117#define PTE_VALID_ARCH(p) \
118 (*((uint32_t *) (p)) != 0)
119#define PTE_PRESENT_ARCH(p) \
120 ((p)->present != 0)
121#define PTE_GET_FRAME_ARCH(p) \
122 ((p)->frame_address << FRAME_WIDTH)
123#define PTE_WRITABLE_ARCH(p) \
124 ((p)->writeable != 0)
[fb84455]125#define PTE_EXECUTABLE_ARCH(p) 1
[ecbdc724]126
[8f2153b]127#ifndef __ASM__
128
[b3f8fb7]129#include <mm/mm.h>
130#include <arch/interrupt.h>
[8f2153b]131
[567807b1]132/* Page fault error codes. */
133
[c03ee1c]134/** When bit on this position is 0, the page fault was caused by a not-present
135 * page.
136 */
[b3f8fb7]137#define PFERR_CODE_P (1 << 0)
[567807b1]138
139/** When bit on this position is 1, the page fault was caused by a write. */
[b3f8fb7]140#define PFERR_CODE_RW (1 << 1)
[567807b1]141
142/** When bit on this position is 1, the page fault was caused in user mode. */
[b3f8fb7]143#define PFERR_CODE_US (1 << 2)
[567807b1]144
145/** When bit on this position is 1, a reserved bit was set in page directory. */
[b3f8fb7]146#define PFERR_CODE_RSVD (1 << 3)
[f761f1eb]147
[ff9f858]148static inline int get_pt_flags(pte_t *pt, index_t i)
149{
150 pte_t *p = &pt[i];
151
[c03ee1c]152 return ((!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT |
153 (!p->present) << PAGE_PRESENT_SHIFT |
154 p->uaccessible << PAGE_USER_SHIFT |
155 1 << PAGE_READ_SHIFT |
156 p->writeable << PAGE_WRITE_SHIFT |
157 1 << PAGE_EXEC_SHIFT |
158 p->global << PAGE_GLOBAL_SHIFT);
[ff9f858]159}
160
161static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
162{
163 pte_t *p = &pt[i];
164
165 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
166 p->present = !(flags & PAGE_NOT_PRESENT);
[51029384]167 p->uaccessible = (flags & PAGE_USER) != 0;
168 p->writeable = (flags & PAGE_WRITE) != 0;
[bfb87df]169 p->global = (flags & PAGE_GLOBAL) != 0;
[0882a9a]170
171 /*
[c03ee1c]172 * Ensure that there is at least one bit set even if the present bit is
173 * cleared.
[0882a9a]174 */
175 p->soft_valid = true;
[ff9f858]176}
[992bbb97]177
[f761f1eb]178extern void page_arch_init(void);
[567807b1]179extern void page_fault(int n, istate_t *istate);
[f761f1eb]180
[8f2153b]181#endif /* __ASM__ */
182
[d1f8a87]183#endif /* KERNEL */
184
[f761f1eb]185#endif
[b45c443]186
[06e1e95]187/** @}
[b45c443]188 */
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