source: mainline/kernel/arch/ia32/include/interrupt.h@ 77385fe

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 77385fe was 77385fe, checked in by Jakub Jermar <jakub@…>, 15 years ago

Reorganize the ia32 istate_t slightly so that it can also be used by the
syscall handlers.

  • Property mode set to 100644
File size: 4.0 KB
RevLine 
[f761f1eb]1/*
[df4ed85]2 * Copyright (c) 2001-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[3222efd]29/** @addtogroup ia32interrupt
[b45c443]30 * @{
31 */
32/** @file
33 */
34
[06e1e95]35#ifndef KERN_ia32_INTERRUPT_H_
36#define KERN_ia32_INTERRUPT_H_
[f761f1eb]37
[d99c1d2]38#include <typedefs.h>
[f761f1eb]39#include <arch/pm.h>
[7a0359b]40#include <trace.h>
[f761f1eb]41
[7a0359b]42#define IVT_ITEMS IDT_ITEMS
43#define IVT_FIRST 0
[f761f1eb]44
[7a0359b]45#define EXC_COUNT 32
46#define IRQ_COUNT 16
[f761f1eb]47
[7a0359b]48#define IVT_EXCBASE 0
49#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT)
50#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT)
[f761f1eb]51
[7a0359b]52#define IRQ_CLK 0
53#define IRQ_KBD 1
54#define IRQ_PIC1 2
55#define IRQ_PIC_SPUR 7
56#define IRQ_MOUSE 12
57#define IRQ_DP8390 9
[f761f1eb]58
[7a0359b]59/* This one must have four least significant bits set to ones */
60#define VECTOR_APIC_SPUR (IVT_ITEMS - 1)
[f761f1eb]61
[cea12e9]62#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
[f761f1eb]63#error Wrong definition of VECTOR_APIC_SPUR
64#endif
65
[7a0359b]66#define VECTOR_DEBUG 1
67#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK)
68#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR)
69#define VECTOR_SYSCALL IVT_FREEBASE
70#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1)
71#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2)
[f761f1eb]72
[8fb47ec0]73typedef struct istate {
[77385fe]74 /*
75 * The strange order of the GPRs is given by the requirement to use the
76 * istate structure for both regular interrupts and exceptions as well
77 * as for syscall handler which use this order as an optimization.
78 */
[7f1c620]79 uint32_t edx;
[77385fe]80 uint32_t ecx;
81 uint32_t ebx;
[6473d41]82 uint32_t esi;
[77385fe]83 uint32_t edi;
[8fb47ec0]84 uint32_t ebp;
[77385fe]85 uint32_t eax;
[6473d41]86
[7a0359b]87 uint32_t ebp_frame; /* imitation of frame pointer linkage */
88 uint32_t eip_frame; /* imitation of return address linkage */
89
[7f1c620]90 uint32_t gs;
91 uint32_t fs;
92 uint32_t es;
93 uint32_t ds;
[7a0359b]94
95 uint32_t error_word; /* real or fake error word */
[7f1c620]96 uint32_t eip;
97 uint32_t cs;
98 uint32_t eflags;
[7a0359b]99 uint32_t esp; /* only if istate_t is from uspace */
100 uint32_t ss; /* only if istate_t is from uspace */
[b3f8fb7]101} istate_t;
[25d7709]102
[874621f]103/** Return true if exception happened while in userspace */
[7a0359b]104NO_TRACE static inline int istate_from_uspace(istate_t *istate)
[874621f]105{
106 return !(istate->eip & 0x80000000);
107}
108
[7a0359b]109NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
110 uintptr_t retaddr)
[e3c762cd]111{
112 istate->eip = retaddr;
113}
114
[7a0359b]115NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
[874621f]116{
117 return istate->eip;
118}
119
[7a0359b]120NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
[8fb47ec0]121{
122 return istate->ebp;
123}
124
[7a0359b]125extern void (* disable_irqs_function)(uint16_t);
126extern void (* enable_irqs_function)(uint16_t);
[f761f1eb]127extern void (* eoi_function)(void);
128
[cea12e9]129extern void interrupt_init(void);
[7a0359b]130extern void trap_virtual_enable_irqs(uint16_t);
131extern void trap_virtual_disable_irqs(uint16_t);
[f761f1eb]132
133#endif
[b45c443]134
[3222efd]135/** @}
[b45c443]136 */
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