source: mainline/kernel/arch/ia32/include/asm.h@ 91ef7cfd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 91ef7cfd was 44c69b66, checked in by Jakub Jermar <jakub@…>, 15 years ago

Make the code in asm.S independent of the interrupt vector used for syscalls.
  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * Copyright (c) 2005 Sergey Bondari
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup ia32
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia32_ASM_H_
37#define KERN_ia32_ASM_H_
38
39#include <arch/pm.h>
40#include <arch/cpu.h>
41#include <typedefs.h>
42#include <config.h>
43#include <trace.h>
44
45extern uint32_t interrupt_handler_size;
46
47/** Halt CPU
48 *
49 * Halt the current CPU.
50 *
51 */
52NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
53{
54 while (true) {
55 asm volatile (
56 "hlt\n"
57 );
58 }
59}
60
61NO_TRACE static inline void cpu_sleep(void)
62{
63 asm volatile (
64 "hlt\n"
65 );
66}
67
68#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
69 { \
70 unative_t res; \
71 asm volatile ( \
72 "movl %%" #reg ", %[res]" \
73 : [res] "=r" (res) \
74 ); \
75 return res; \
76 }
77
78#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
79 { \
80 asm volatile ( \
81 "movl %[regn], %%" #reg \
82 :: [regn] "r" (regn) \
83 ); \
84 }
85
86GEN_READ_REG(cr0)
87GEN_READ_REG(cr2)
88GEN_READ_REG(cr3)
89GEN_WRITE_REG(cr3)
90
91GEN_READ_REG(dr0)
92GEN_READ_REG(dr1)
93GEN_READ_REG(dr2)
94GEN_READ_REG(dr3)
95GEN_READ_REG(dr6)
96GEN_READ_REG(dr7)
97
98GEN_WRITE_REG(dr0)
99GEN_WRITE_REG(dr1)
100GEN_WRITE_REG(dr2)
101GEN_WRITE_REG(dr3)
102GEN_WRITE_REG(dr6)
103GEN_WRITE_REG(dr7)
104
105/** Byte to port
106 *
107 * Output byte to port
108 *
109 * @param port Port to write to
110 * @param val Value to write
111 *
112 */
113NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
114{
115 asm volatile (
116 "outb %b[val], %w[port]\n"
117 :: [val] "a" (val),
118 [port] "d" (port)
119 );
120}
121
122/** Word to port
123 *
124 * Output word to port
125 *
126 * @param port Port to write to
127 * @param val Value to write
128 *
129 */
130NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
131{
132 asm volatile (
133 "outw %w[val], %w[port]\n"
134 :: [val] "a" (val),
135 [port] "d" (port)
136 );
137}
138
139/** Double word to port
140 *
141 * Output double word to port
142 *
143 * @param port Port to write to
144 * @param val Value to write
145 *
146 */
147NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
148{
149 asm volatile (
150 "outl %[val], %w[port]\n"
151 :: [val] "a" (val),
152 [port] "d" (port)
153 );
154}
155
156/** Byte from port
157 *
158 * Get byte from port
159 *
160 * @param port Port to read from
161 * @return Value read
162 *
163 */
164NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
165{
166 uint8_t val;
167
168 asm volatile (
169 "inb %w[port], %b[val]\n"
170 : [val] "=a" (val)
171 : [port] "d" (port)
172 );
173
174 return val;
175}
176
177/** Word from port
178 *
179 * Get word from port
180 *
181 * @param port Port to read from
182 * @return Value read
183 *
184 */
185NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
186{
187 uint16_t val;
188
189 asm volatile (
190 "inw %w[port], %w[val]\n"
191 : [val] "=a" (val)
192 : [port] "d" (port)
193 );
194
195 return val;
196}
197
198/** Double word from port
199 *
200 * Get double word from port
201 *
202 * @param port Port to read from
203 * @return Value read
204 *
205 */
206NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
207{
208 uint32_t val;
209
210 asm volatile (
211 "inl %w[port], %[val]\n"
212 : [val] "=a" (val)
213 : [port] "d" (port)
214 );
215
216 return val;
217}
218
219/** Enable interrupts.
220 *
221 * Enable interrupts and return previous
222 * value of EFLAGS.
223 *
224 * @return Old interrupt priority level.
225 *
226 */
227NO_TRACE static inline ipl_t interrupts_enable(void)
228{
229 ipl_t v;
230
231 asm volatile (
232 "pushf\n"
233 "popl %[v]\n"
234 "sti\n"
235 : [v] "=r" (v)
236 );
237
238 return v;
239}
240
241/** Disable interrupts.
242 *
243 * Disable interrupts and return previous
244 * value of EFLAGS.
245 *
246 * @return Old interrupt priority level.
247 *
248 */
249NO_TRACE static inline ipl_t interrupts_disable(void)
250{
251 ipl_t v;
252
253 asm volatile (
254 "pushf\n"
255 "popl %[v]\n"
256 "cli\n"
257 : [v] "=r" (v)
258 );
259
260 return v;
261}
262
263/** Restore interrupt priority level.
264 *
265 * Restore EFLAGS.
266 *
267 * @param ipl Saved interrupt priority level.
268 *
269 */
270NO_TRACE static inline void interrupts_restore(ipl_t ipl)
271{
272 asm volatile (
273 "pushl %[ipl]\n"
274 "popf\n"
275 :: [ipl] "r" (ipl)
276 );
277}
278
279/** Return interrupt priority level.
280 *
281 * @return EFLAFS.
282 *
283 */
284NO_TRACE static inline ipl_t interrupts_read(void)
285{
286 ipl_t v;
287
288 asm volatile (
289 "pushf\n"
290 "popl %[v]\n"
291 : [v] "=r" (v)
292 );
293
294 return v;
295}
296
297/** Check interrupts state.
298 *
299 * @return True if interrupts are disabled.
300 *
301 */
302NO_TRACE static inline bool interrupts_disabled(void)
303{
304 ipl_t v;
305
306 asm volatile (
307 "pushf\n"
308 "popl %[v]\n"
309 : [v] "=r" (v)
310 );
311
312 return ((v & EFLAGS_IF) == 0);
313}
314
315/** Write to MSR */
316NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
317{
318 asm volatile (
319 "wrmsr"
320 :: "c" (msr),
321 "a" ((uint32_t) (value)),
322 "d" ((uint32_t) (value >> 32))
323 );
324}
325
326NO_TRACE static inline uint64_t read_msr(uint32_t msr)
327{
328 uint32_t ax, dx;
329
330 asm volatile (
331 "rdmsr"
332 : "=a" (ax),
333 "=d" (dx)
334 : "c" (msr)
335 );
336
337 return ((uint64_t) dx << 32) | ax;
338}
339
340
341/** Return base address of current stack
342 *
343 * Return the base address of the current stack.
344 * The stack is assumed to be STACK_SIZE bytes long.
345 * The stack must start on page boundary.
346 *
347 */
348NO_TRACE static inline uintptr_t get_stack_base(void)
349{
350 uintptr_t v;
351
352 asm volatile (
353 "andl %%esp, %[v]\n"
354 : [v] "=r" (v)
355 : "0" (~(STACK_SIZE - 1))
356 );
357
358 return v;
359}
360
361/** Invalidate TLB Entry.
362 *
363 * @param addr Address on a page whose TLB entry is to be invalidated.
364 *
365 */
366NO_TRACE static inline void invlpg(uintptr_t addr)
367{
368 asm volatile (
369 "invlpg %[addr]\n"
370 :: [addr] "m" (*(unative_t *) addr)
371 );
372}
373
374/** Load GDTR register from memory.
375 *
376 * @param gdtr_reg Address of memory from where to load GDTR.
377 *
378 */
379NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
380{
381 asm volatile (
382 "lgdtl %[gdtr_reg]\n"
383 :: [gdtr_reg] "m" (*gdtr_reg)
384 );
385}
386
387/** Store GDTR register to memory.
388 *
389 * @param gdtr_reg Address of memory to where to load GDTR.
390 *
391 */
392NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
393{
394 asm volatile (
395 "sgdtl %[gdtr_reg]\n"
396 : [gdtr_reg] "=m" (*gdtr_reg)
397 );
398}
399
400/** Load IDTR register from memory.
401 *
402 * @param idtr_reg Address of memory from where to load IDTR.
403 *
404 */
405NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
406{
407 asm volatile (
408 "lidtl %[idtr_reg]\n"
409 :: [idtr_reg] "m" (*idtr_reg)
410 );
411}
412
413/** Load TR from descriptor table.
414 *
415 * @param sel Selector specifying descriptor of TSS segment.
416 *
417 */
418NO_TRACE static inline void tr_load(uint16_t sel)
419{
420 asm volatile (
421 "ltr %[sel]"
422 :: [sel] "r" (sel)
423 );
424}
425
426extern void paging_on(void);
427extern void enable_l_apic_in_msr(void);
428
429extern void asm_delay_loop(uint32_t);
430extern void asm_fake_loop(uint32_t);
431
432extern uintptr_t int_syscall;
433
434extern uintptr_t int_0;
435extern uintptr_t int_1;
436extern uintptr_t int_2;
437extern uintptr_t int_3;
438extern uintptr_t int_4;
439extern uintptr_t int_5;
440extern uintptr_t int_6;
441extern uintptr_t int_7;
442extern uintptr_t int_8;
443extern uintptr_t int_9;
444extern uintptr_t int_10;
445extern uintptr_t int_11;
446extern uintptr_t int_12;
447extern uintptr_t int_13;
448extern uintptr_t int_14;
449extern uintptr_t int_15;
450extern uintptr_t int_16;
451extern uintptr_t int_17;
452extern uintptr_t int_18;
453extern uintptr_t int_19;
454extern uintptr_t int_20;
455extern uintptr_t int_21;
456extern uintptr_t int_22;
457extern uintptr_t int_23;
458extern uintptr_t int_24;
459extern uintptr_t int_25;
460extern uintptr_t int_26;
461extern uintptr_t int_27;
462extern uintptr_t int_28;
463extern uintptr_t int_29;
464extern uintptr_t int_30;
465extern uintptr_t int_31;
466extern uintptr_t int_32;
467extern uintptr_t int_33;
468extern uintptr_t int_34;
469extern uintptr_t int_35;
470extern uintptr_t int_36;
471extern uintptr_t int_37;
472extern uintptr_t int_38;
473extern uintptr_t int_39;
474extern uintptr_t int_40;
475extern uintptr_t int_41;
476extern uintptr_t int_42;
477extern uintptr_t int_43;
478extern uintptr_t int_44;
479extern uintptr_t int_45;
480extern uintptr_t int_46;
481extern uintptr_t int_47;
482extern uintptr_t int_48;
483extern uintptr_t int_49;
484extern uintptr_t int_50;
485extern uintptr_t int_51;
486extern uintptr_t int_52;
487extern uintptr_t int_53;
488extern uintptr_t int_54;
489extern uintptr_t int_55;
490extern uintptr_t int_56;
491extern uintptr_t int_57;
492extern uintptr_t int_58;
493extern uintptr_t int_59;
494extern uintptr_t int_60;
495extern uintptr_t int_61;
496extern uintptr_t int_62;
497extern uintptr_t int_63;
498
499#endif
500
501/** @}
502 */
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