source: mainline/kernel/arch/ia32/include/asm.h@ 28a6190

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 28a6190 was c22531fc, checked in by Martin Decky <martin@…>, 14 years ago

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1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * Copyright (c) 2005 Sergey Bondari
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup ia32
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia32_ASM_H_
37#define KERN_ia32_ASM_H_
38
39#include <arch/pm.h>
40#include <arch/cpu.h>
41#include <typedefs.h>
42#include <config.h>
43#include <trace.h>
44
45/** Halt CPU
46 *
47 * Halt the current CPU.
48 *
49 */
50NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
51{
52 while (true) {
53 asm volatile (
54 "hlt\n"
55 );
56 }
57}
58
59NO_TRACE static inline void cpu_sleep(void)
60{
61 asm volatile (
62 "hlt\n"
63 );
64}
65
66#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
67 { \
68 sysarg_t res; \
69 asm volatile ( \
70 "movl %%" #reg ", %[res]" \
71 : [res] "=r" (res) \
72 ); \
73 return res; \
74 }
75
76#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
77 { \
78 asm volatile ( \
79 "movl %[regn], %%" #reg \
80 :: [regn] "r" (regn) \
81 ); \
82 }
83
84GEN_READ_REG(cr0)
85GEN_READ_REG(cr2)
86GEN_READ_REG(cr3)
87GEN_WRITE_REG(cr3)
88
89GEN_READ_REG(dr0)
90GEN_READ_REG(dr1)
91GEN_READ_REG(dr2)
92GEN_READ_REG(dr3)
93GEN_READ_REG(dr6)
94GEN_READ_REG(dr7)
95
96GEN_WRITE_REG(dr0)
97GEN_WRITE_REG(dr1)
98GEN_WRITE_REG(dr2)
99GEN_WRITE_REG(dr3)
100GEN_WRITE_REG(dr6)
101GEN_WRITE_REG(dr7)
102
103#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
104
105/** Byte to port
106 *
107 * Output byte to port
108 *
109 * @param port Port to write to
110 * @param val Value to write
111 *
112 */
113NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
114{
115 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
116 asm volatile (
117 "outb %b[val], %w[port]\n"
118 :: [val] "a" (val), [port] "d" (port)
119 );
120 } else
121 *port = val;
122}
123
124/** Word to port
125 *
126 * Output word to port
127 *
128 * @param port Port to write to
129 * @param val Value to write
130 *
131 */
132NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
133{
134 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
135 asm volatile (
136 "outw %w[val], %w[port]\n"
137 :: [val] "a" (val), [port] "d" (port)
138 );
139 } else
140 *port = val;
141}
142
143/** Double word to port
144 *
145 * Output double word to port
146 *
147 * @param port Port to write to
148 * @param val Value to write
149 *
150 */
151NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
152{
153 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
154 asm volatile (
155 "outl %[val], %w[port]\n"
156 :: [val] "a" (val), [port] "d" (port)
157 );
158 } else
159 *port = val;
160}
161
162/** Byte from port
163 *
164 * Get byte from port
165 *
166 * @param port Port to read from
167 * @return Value read
168 *
169 */
170NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
171{
172 if (((void *)port) < IO_SPACE_BOUNDARY) {
173 uint8_t val;
174
175 asm volatile (
176 "inb %w[port], %b[val]\n"
177 : [val] "=a" (val)
178 : [port] "d" (port)
179 );
180
181 return val;
182 } else
183 return (uint8_t) *port;
184}
185
186/** Word from port
187 *
188 * Get word from port
189 *
190 * @param port Port to read from
191 * @return Value read
192 *
193 */
194NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
195{
196 if (((void *)port) < IO_SPACE_BOUNDARY) {
197 uint16_t val;
198
199 asm volatile (
200 "inw %w[port], %w[val]\n"
201 : [val] "=a" (val)
202 : [port] "d" (port)
203 );
204
205 return val;
206 } else
207 return (uint16_t) *port;
208}
209
210/** Double word from port
211 *
212 * Get double word from port
213 *
214 * @param port Port to read from
215 * @return Value read
216 *
217 */
218NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
219{
220 if (((void *)port) < IO_SPACE_BOUNDARY) {
221 uint32_t val;
222
223 asm volatile (
224 "inl %w[port], %[val]\n"
225 : [val] "=a" (val)
226 : [port] "d" (port)
227 );
228
229 return val;
230 } else
231 return (uint32_t) *port;
232}
233
234/** Enable interrupts.
235 *
236 * Enable interrupts and return previous
237 * value of EFLAGS.
238 *
239 * @return Old interrupt priority level.
240 *
241 */
242NO_TRACE static inline ipl_t interrupts_enable(void)
243{
244 ipl_t v;
245
246 asm volatile (
247 "pushf\n"
248 "popl %[v]\n"
249 "sti\n"
250 : [v] "=r" (v)
251 );
252
253 return v;
254}
255
256/** Disable interrupts.
257 *
258 * Disable interrupts and return previous
259 * value of EFLAGS.
260 *
261 * @return Old interrupt priority level.
262 *
263 */
264NO_TRACE static inline ipl_t interrupts_disable(void)
265{
266 ipl_t v;
267
268 asm volatile (
269 "pushf\n"
270 "popl %[v]\n"
271 "cli\n"
272 : [v] "=r" (v)
273 );
274
275 return v;
276}
277
278/** Restore interrupt priority level.
279 *
280 * Restore EFLAGS.
281 *
282 * @param ipl Saved interrupt priority level.
283 *
284 */
285NO_TRACE static inline void interrupts_restore(ipl_t ipl)
286{
287 asm volatile (
288 "pushl %[ipl]\n"
289 "popf\n"
290 :: [ipl] "r" (ipl)
291 );
292}
293
294/** Return interrupt priority level.
295 *
296 * @return EFLAFS.
297 *
298 */
299NO_TRACE static inline ipl_t interrupts_read(void)
300{
301 ipl_t v;
302
303 asm volatile (
304 "pushf\n"
305 "popl %[v]\n"
306 : [v] "=r" (v)
307 );
308
309 return v;
310}
311
312/** Check interrupts state.
313 *
314 * @return True if interrupts are disabled.
315 *
316 */
317NO_TRACE static inline bool interrupts_disabled(void)
318{
319 ipl_t v;
320
321 asm volatile (
322 "pushf\n"
323 "popl %[v]\n"
324 : [v] "=r" (v)
325 );
326
327 return ((v & EFLAGS_IF) == 0);
328}
329
330#ifndef PROCESSOR_i486
331
332/** Write to MSR */
333NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
334{
335 asm volatile (
336 "wrmsr"
337 :: "c" (msr),
338 "a" ((uint32_t) (value)),
339 "d" ((uint32_t) (value >> 32))
340 );
341}
342
343NO_TRACE static inline uint64_t read_msr(uint32_t msr)
344{
345 uint32_t ax, dx;
346
347 asm volatile (
348 "rdmsr"
349 : "=a" (ax),
350 "=d" (dx)
351 : "c" (msr)
352 );
353
354 return ((uint64_t) dx << 32) | ax;
355}
356
357#endif /* PROCESSOR_i486 */
358
359
360/** Return base address of current stack
361 *
362 * Return the base address of the current stack.
363 * The stack is assumed to be STACK_SIZE bytes long.
364 * The stack must start on page boundary.
365 *
366 */
367NO_TRACE static inline uintptr_t get_stack_base(void)
368{
369 uintptr_t v;
370
371 asm volatile (
372 "andl %%esp, %[v]\n"
373 : [v] "=r" (v)
374 : "0" (~(STACK_SIZE - 1))
375 );
376
377 return v;
378}
379
380/** Invalidate TLB Entry.
381 *
382 * @param addr Address on a page whose TLB entry is to be invalidated.
383 *
384 */
385NO_TRACE static inline void invlpg(uintptr_t addr)
386{
387 asm volatile (
388 "invlpg %[addr]\n"
389 :: [addr] "m" (*(sysarg_t *) addr)
390 );
391}
392
393/** Load GDTR register from memory.
394 *
395 * @param gdtr_reg Address of memory from where to load GDTR.
396 *
397 */
398NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
399{
400 asm volatile (
401 "lgdtl %[gdtr_reg]\n"
402 :: [gdtr_reg] "m" (*gdtr_reg)
403 );
404}
405
406/** Store GDTR register to memory.
407 *
408 * @param gdtr_reg Address of memory to where to load GDTR.
409 *
410 */
411NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
412{
413 asm volatile (
414 "sgdtl %[gdtr_reg]\n"
415 : [gdtr_reg] "=m" (*gdtr_reg)
416 );
417}
418
419/** Load IDTR register from memory.
420 *
421 * @param idtr_reg Address of memory from where to load IDTR.
422 *
423 */
424NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
425{
426 asm volatile (
427 "lidtl %[idtr_reg]\n"
428 :: [idtr_reg] "m" (*idtr_reg)
429 );
430}
431
432/** Load TR from descriptor table.
433 *
434 * @param sel Selector specifying descriptor of TSS segment.
435 *
436 */
437NO_TRACE static inline void tr_load(uint16_t sel)
438{
439 asm volatile (
440 "ltr %[sel]"
441 :: [sel] "r" (sel)
442 );
443}
444
445extern void paging_on(void);
446extern void enable_l_apic_in_msr(void);
447
448extern void asm_delay_loop(uint32_t);
449extern void asm_fake_loop(uint32_t);
450
451extern uintptr_t int_syscall;
452
453extern uintptr_t int_0;
454extern uintptr_t int_1;
455extern uintptr_t int_2;
456extern uintptr_t int_3;
457extern uintptr_t int_4;
458extern uintptr_t int_5;
459extern uintptr_t int_6;
460extern uintptr_t int_7;
461extern uintptr_t int_8;
462extern uintptr_t int_9;
463extern uintptr_t int_10;
464extern uintptr_t int_11;
465extern uintptr_t int_12;
466extern uintptr_t int_13;
467extern uintptr_t int_14;
468extern uintptr_t int_15;
469extern uintptr_t int_16;
470extern uintptr_t int_17;
471extern uintptr_t int_18;
472extern uintptr_t int_19;
473extern uintptr_t int_20;
474extern uintptr_t int_21;
475extern uintptr_t int_22;
476extern uintptr_t int_23;
477extern uintptr_t int_24;
478extern uintptr_t int_25;
479extern uintptr_t int_26;
480extern uintptr_t int_27;
481extern uintptr_t int_28;
482extern uintptr_t int_29;
483extern uintptr_t int_30;
484extern uintptr_t int_31;
485extern uintptr_t int_32;
486extern uintptr_t int_33;
487extern uintptr_t int_34;
488extern uintptr_t int_35;
489extern uintptr_t int_36;
490extern uintptr_t int_37;
491extern uintptr_t int_38;
492extern uintptr_t int_39;
493extern uintptr_t int_40;
494extern uintptr_t int_41;
495extern uintptr_t int_42;
496extern uintptr_t int_43;
497extern uintptr_t int_44;
498extern uintptr_t int_45;
499extern uintptr_t int_46;
500extern uintptr_t int_47;
501extern uintptr_t int_48;
502extern uintptr_t int_49;
503extern uintptr_t int_50;
504extern uintptr_t int_51;
505extern uintptr_t int_52;
506extern uintptr_t int_53;
507extern uintptr_t int_54;
508extern uintptr_t int_55;
509extern uintptr_t int_56;
510extern uintptr_t int_57;
511extern uintptr_t int_58;
512extern uintptr_t int_59;
513extern uintptr_t int_60;
514extern uintptr_t int_61;
515extern uintptr_t int_62;
516extern uintptr_t int_63;
517
518#endif
519
520/** @}
521 */
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