source: mainline/kernel/arch/ia32/include/arch/asm.h@ 2b264c4

ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2b264c4 was 2b264c4, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 3 years ago

Add architecture-specific spinlock optimization
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * Copyright (c) 2005 Sergey Bondari
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup kernel_ia32
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia32_ASM_H_
37#define KERN_ia32_ASM_H_
38
39#include <arch/pm.h>
40#include <arch/cpu.h>
41#include <typedefs.h>
42#include <config.h>
43#include <trace.h>
44
45/** Halt CPU
46 *
47 * Halt the current CPU.
48 *
49 */
50_NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
51{
52 while (true) {
53 asm volatile (
54 "hlt\n"
55 );
56 }
57}
58
59_NO_TRACE static inline void cpu_sleep(void)
60{
61 asm volatile (
62 "hlt\n"
63 );
64}
65
66#define ARCH_SPIN_HINT() asm volatile ("pause\n")
67
68#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
69 { \
70 sysarg_t res; \
71 asm volatile ( \
72 "movl %%" #reg ", %[res]" \
73 : [res] "=r" (res) \
74 ); \
75 return res; \
76 }
77
78#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
79 { \
80 asm volatile ( \
81 "movl %[regn], %%" #reg \
82 :: [regn] "r" (regn) \
83 ); \
84 }
85
86GEN_READ_REG(cr0);
87GEN_READ_REG(cr2);
88GEN_READ_REG(cr3);
89GEN_WRITE_REG(cr3);
90
91GEN_WRITE_REG(cr0);
92
93GEN_READ_REG(dr0);
94GEN_READ_REG(dr1);
95GEN_READ_REG(dr2);
96GEN_READ_REG(dr3);
97GEN_READ_REG(dr6);
98GEN_READ_REG(dr7);
99
100GEN_WRITE_REG(dr0);
101GEN_WRITE_REG(dr1);
102GEN_WRITE_REG(dr2);
103GEN_WRITE_REG(dr3);
104GEN_WRITE_REG(dr6);
105GEN_WRITE_REG(dr7);
106
107#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
108
109/** Byte to port
110 *
111 * Output byte to port
112 *
113 * @param port Port to write to
114 * @param val Value to write
115 *
116 */
117_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
118{
119 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
120 asm volatile (
121 "outb %b[val], %w[port]\n"
122 :: [val] "a" (val), [port] "d" (port)
123 );
124 } else
125 *port = val;
126}
127
128/** Word to port
129 *
130 * Output word to port
131 *
132 * @param port Port to write to
133 * @param val Value to write
134 *
135 */
136_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
137{
138 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
139 asm volatile (
140 "outw %w[val], %w[port]\n"
141 :: [val] "a" (val), [port] "d" (port)
142 );
143 } else
144 *port = val;
145}
146
147/** Double word to port
148 *
149 * Output double word to port
150 *
151 * @param port Port to write to
152 * @param val Value to write
153 *
154 */
155_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
156{
157 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
158 asm volatile (
159 "outl %[val], %w[port]\n"
160 :: [val] "a" (val), [port] "d" (port)
161 );
162 } else
163 *port = val;
164}
165
166/** Byte from port
167 *
168 * Get byte from port
169 *
170 * @param port Port to read from
171 * @return Value read
172 *
173 */
174_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
175{
176 if (((void *)port) < IO_SPACE_BOUNDARY) {
177 uint8_t val;
178
179 asm volatile (
180 "inb %w[port], %b[val]\n"
181 : [val] "=a" (val)
182 : [port] "d" (port)
183 );
184
185 return val;
186 } else
187 return (uint8_t) *port;
188}
189
190/** Word from port
191 *
192 * Get word from port
193 *
194 * @param port Port to read from
195 * @return Value read
196 *
197 */
198_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
199{
200 if (((void *)port) < IO_SPACE_BOUNDARY) {
201 uint16_t val;
202
203 asm volatile (
204 "inw %w[port], %w[val]\n"
205 : [val] "=a" (val)
206 : [port] "d" (port)
207 );
208
209 return val;
210 } else
211 return (uint16_t) *port;
212}
213
214/** Double word from port
215 *
216 * Get double word from port
217 *
218 * @param port Port to read from
219 * @return Value read
220 *
221 */
222_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
223{
224 if (((void *)port) < IO_SPACE_BOUNDARY) {
225 uint32_t val;
226
227 asm volatile (
228 "inl %w[port], %[val]\n"
229 : [val] "=a" (val)
230 : [port] "d" (port)
231 );
232
233 return val;
234 } else
235 return (uint32_t) *port;
236}
237
238_NO_TRACE static inline uint32_t read_eflags(void)
239{
240 uint32_t eflags;
241
242 asm volatile (
243 "pushf\n"
244 "popl %[v]\n"
245 : [v] "=r" (eflags)
246 );
247
248 return eflags;
249}
250
251_NO_TRACE static inline void write_eflags(uint32_t eflags)
252{
253 asm volatile (
254 "pushl %[v]\n"
255 "popf\n"
256 :: [v] "r" (eflags)
257 );
258}
259
260/** Return interrupt priority level.
261 *
262 * @return Current interrupt priority level.
263 *
264 */
265_NO_TRACE static inline ipl_t interrupts_read(void)
266{
267 return (ipl_t) read_eflags();
268}
269
270/** Enable interrupts.
271 *
272 * Enable interrupts and return the previous interrupt priority level.
273 *
274 * @return Old interrupt priority level.
275 *
276 */
277_NO_TRACE static inline ipl_t interrupts_enable(void)
278{
279 ipl_t ipl = interrupts_read();
280
281 asm volatile ("sti\n");
282
283 return ipl;
284}
285
286/** Disable interrupts.
287 *
288 * Disable interrupts and return the previous interrupt priority level.
289 *
290 * @return Old interrupt priority level.
291 *
292 */
293_NO_TRACE static inline ipl_t interrupts_disable(void)
294{
295 ipl_t ipl = interrupts_read();
296
297 asm volatile ("cli\n");
298
299 return ipl;
300}
301
302/** Restore interrupt priority level.
303 *
304 * Restore a saved interrupt priority level.
305 *
306 * @param ipl Saved interrupt priority level.
307 *
308 */
309_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
310{
311 write_eflags((uint32_t) ipl);
312}
313
314/** Check interrupts state.
315 *
316 * @return True if interrupts are disabled.
317 *
318 */
319_NO_TRACE static inline bool interrupts_disabled(void)
320{
321 return ((read_eflags() & EFLAGS_IF) == 0);
322}
323
324#ifndef PROCESSOR_i486
325
326/** Write to MSR */
327_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
328{
329 asm volatile (
330 "wrmsr"
331 :: "c" (msr),
332 "a" ((uint32_t) (value)),
333 "d" ((uint32_t) (value >> 32))
334 );
335}
336
337_NO_TRACE static inline uint64_t read_msr(uint32_t msr)
338{
339 uint32_t ax, dx;
340
341 asm volatile (
342 "rdmsr"
343 : "=a" (ax),
344 "=d" (dx)
345 : "c" (msr)
346 );
347
348 return ((uint64_t) dx << 32) | ax;
349}
350
351#endif /* PROCESSOR_i486 */
352
353/** Invalidate TLB Entry.
354 *
355 * @param addr Address on a page whose TLB entry is to be invalidated.
356 *
357 */
358_NO_TRACE static inline void invlpg(uintptr_t addr)
359{
360 asm volatile (
361 "invlpg %[addr]\n"
362 :: [addr] "m" (*(sysarg_t *) addr)
363 );
364}
365
366/** Load GDTR register from memory.
367 *
368 * @param gdtr_reg Address of memory from where to load GDTR.
369 *
370 */
371_NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
372{
373 asm volatile (
374 "lgdtl %[gdtr_reg]\n"
375 :: [gdtr_reg] "m" (*gdtr_reg)
376 );
377}
378
379/** Store GDTR register to memory.
380 *
381 * @param gdtr_reg Address of memory to where to load GDTR.
382 *
383 */
384_NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
385{
386 asm volatile (
387 "sgdtl %[gdtr_reg]\n"
388 : [gdtr_reg] "=m" (*gdtr_reg)
389 );
390}
391
392/** Load IDTR register from memory.
393 *
394 * @param idtr_reg Address of memory from where to load IDTR.
395 *
396 */
397_NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
398{
399 asm volatile (
400 "lidtl %[idtr_reg]\n"
401 :: [idtr_reg] "m" (*idtr_reg)
402 );
403}
404
405/** Load TR from descriptor table.
406 *
407 * @param sel Selector specifying descriptor of TSS segment.
408 *
409 */
410_NO_TRACE static inline void tr_load(uint16_t sel)
411{
412 asm volatile (
413 "ltr %[sel]"
414 :: [sel] "r" (sel)
415 );
416}
417
418/** Load GS from descriptor table.
419 *
420 * @param sel Selector specifying descriptor of the GS segment.
421 *
422 */
423_NO_TRACE static inline void gs_load(uint16_t sel)
424{
425 asm volatile (
426 "mov %[sel], %%gs"
427 :: [sel] "r" (sel)
428 );
429}
430
431extern void paging_on(void);
432extern void enable_l_apic_in_msr(void);
433
434extern void asm_delay_loop(uint32_t);
435extern void asm_fake_loop(uint32_t);
436
437extern uintptr_t int_syscall;
438
439extern uintptr_t int_0;
440extern uintptr_t int_1;
441extern uintptr_t int_2;
442extern uintptr_t int_3;
443extern uintptr_t int_4;
444extern uintptr_t int_5;
445extern uintptr_t int_6;
446extern uintptr_t int_7;
447extern uintptr_t int_8;
448extern uintptr_t int_9;
449extern uintptr_t int_10;
450extern uintptr_t int_11;
451extern uintptr_t int_12;
452extern uintptr_t int_13;
453extern uintptr_t int_14;
454extern uintptr_t int_15;
455extern uintptr_t int_16;
456extern uintptr_t int_17;
457extern uintptr_t int_18;
458extern uintptr_t int_19;
459extern uintptr_t int_20;
460extern uintptr_t int_21;
461extern uintptr_t int_22;
462extern uintptr_t int_23;
463extern uintptr_t int_24;
464extern uintptr_t int_25;
465extern uintptr_t int_26;
466extern uintptr_t int_27;
467extern uintptr_t int_28;
468extern uintptr_t int_29;
469extern uintptr_t int_30;
470extern uintptr_t int_31;
471extern uintptr_t int_32;
472extern uintptr_t int_33;
473extern uintptr_t int_34;
474extern uintptr_t int_35;
475extern uintptr_t int_36;
476extern uintptr_t int_37;
477extern uintptr_t int_38;
478extern uintptr_t int_39;
479extern uintptr_t int_40;
480extern uintptr_t int_41;
481extern uintptr_t int_42;
482extern uintptr_t int_43;
483extern uintptr_t int_44;
484extern uintptr_t int_45;
485extern uintptr_t int_46;
486extern uintptr_t int_47;
487extern uintptr_t int_48;
488extern uintptr_t int_49;
489extern uintptr_t int_50;
490extern uintptr_t int_51;
491extern uintptr_t int_52;
492extern uintptr_t int_53;
493extern uintptr_t int_54;
494extern uintptr_t int_55;
495extern uintptr_t int_56;
496extern uintptr_t int_57;
497extern uintptr_t int_58;
498extern uintptr_t int_59;
499extern uintptr_t int_60;
500extern uintptr_t int_61;
501extern uintptr_t int_62;
502extern uintptr_t int_63;
503
504#endif
505
506/** @}
507 */
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