source: mainline/kernel/arch/ia32/include/arch/asm.h@ 128359eb

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 128359eb was 128359eb, checked in by Martin Decky <martin@…>, 6 years ago

Replace get_stack_base() with builtin_frame_address(0)

The usage of an intrinsic function to obtain the current stack pointer
should provide the compuler more room for performance optimizations than
the hand-written (and volatile) inline assembly block.
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * Copyright (c) 2001-2004 Jakub Jermar
3 * Copyright (c) 2005 Sergey Bondari
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup kernel_ia32
31 * @{
32 */
33/** @file
34 */
35
36#ifndef KERN_ia32_ASM_H_
37#define KERN_ia32_ASM_H_
38
39#include <arch/pm.h>
40#include <arch/cpu.h>
41#include <typedefs.h>
42#include <config.h>
43#include <trace.h>
44
45/** Halt CPU
46 *
47 * Halt the current CPU.
48 *
49 */
50_NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
51{
52 while (true) {
53 asm volatile (
54 "hlt\n"
55 );
56 }
57}
58
59_NO_TRACE static inline void cpu_sleep(void)
60{
61 asm volatile (
62 "hlt\n"
63 );
64}
65
66#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
67 { \
68 sysarg_t res; \
69 asm volatile ( \
70 "movl %%" #reg ", %[res]" \
71 : [res] "=r" (res) \
72 ); \
73 return res; \
74 }
75
76#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
77 { \
78 asm volatile ( \
79 "movl %[regn], %%" #reg \
80 :: [regn] "r" (regn) \
81 ); \
82 }
83
84GEN_READ_REG(cr0);
85GEN_READ_REG(cr2);
86GEN_READ_REG(cr3);
87GEN_WRITE_REG(cr3);
88
89GEN_WRITE_REG(cr0);
90
91GEN_READ_REG(dr0);
92GEN_READ_REG(dr1);
93GEN_READ_REG(dr2);
94GEN_READ_REG(dr3);
95GEN_READ_REG(dr6);
96GEN_READ_REG(dr7);
97
98GEN_WRITE_REG(dr0);
99GEN_WRITE_REG(dr1);
100GEN_WRITE_REG(dr2);
101GEN_WRITE_REG(dr3);
102GEN_WRITE_REG(dr6);
103GEN_WRITE_REG(dr7);
104
105#define IO_SPACE_BOUNDARY ((void *) (64 * 1024))
106
107/** Byte to port
108 *
109 * Output byte to port
110 *
111 * @param port Port to write to
112 * @param val Value to write
113 *
114 */
115_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
116{
117 if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
118 asm volatile (
119 "outb %b[val], %w[port]\n"
120 :: [val] "a" (val), [port] "d" (port)
121 );
122 } else
123 *port = val;
124}
125
126/** Word to port
127 *
128 * Output word to port
129 *
130 * @param port Port to write to
131 * @param val Value to write
132 *
133 */
134_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
135{
136 if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
137 asm volatile (
138 "outw %w[val], %w[port]\n"
139 :: [val] "a" (val), [port] "d" (port)
140 );
141 } else
142 *port = val;
143}
144
145/** Double word to port
146 *
147 * Output double word to port
148 *
149 * @param port Port to write to
150 * @param val Value to write
151 *
152 */
153_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
154{
155 if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
156 asm volatile (
157 "outl %[val], %w[port]\n"
158 :: [val] "a" (val), [port] "d" (port)
159 );
160 } else
161 *port = val;
162}
163
164/** Byte from port
165 *
166 * Get byte from port
167 *
168 * @param port Port to read from
169 * @return Value read
170 *
171 */
172_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
173{
174 if (((void *)port) < IO_SPACE_BOUNDARY) {
175 uint8_t val;
176
177 asm volatile (
178 "inb %w[port], %b[val]\n"
179 : [val] "=a" (val)
180 : [port] "d" (port)
181 );
182
183 return val;
184 } else
185 return (uint8_t) *port;
186}
187
188/** Word from port
189 *
190 * Get word from port
191 *
192 * @param port Port to read from
193 * @return Value read
194 *
195 */
196_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
197{
198 if (((void *)port) < IO_SPACE_BOUNDARY) {
199 uint16_t val;
200
201 asm volatile (
202 "inw %w[port], %w[val]\n"
203 : [val] "=a" (val)
204 : [port] "d" (port)
205 );
206
207 return val;
208 } else
209 return (uint16_t) *port;
210}
211
212/** Double word from port
213 *
214 * Get double word from port
215 *
216 * @param port Port to read from
217 * @return Value read
218 *
219 */
220_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
221{
222 if (((void *)port) < IO_SPACE_BOUNDARY) {
223 uint32_t val;
224
225 asm volatile (
226 "inl %w[port], %[val]\n"
227 : [val] "=a" (val)
228 : [port] "d" (port)
229 );
230
231 return val;
232 } else
233 return (uint32_t) *port;
234}
235
236_NO_TRACE static inline uint32_t read_eflags(void)
237{
238 uint32_t eflags;
239
240 asm volatile (
241 "pushf\n"
242 "popl %[v]\n"
243 : [v] "=r" (eflags)
244 );
245
246 return eflags;
247}
248
249_NO_TRACE static inline void write_eflags(uint32_t eflags)
250{
251 asm volatile (
252 "pushl %[v]\n"
253 "popf\n"
254 :: [v] "r" (eflags)
255 );
256}
257
258/** Return interrupt priority level.
259 *
260 * @return Current interrupt priority level.
261 *
262 */
263_NO_TRACE static inline ipl_t interrupts_read(void)
264{
265 return (ipl_t) read_eflags();
266}
267
268/** Enable interrupts.
269 *
270 * Enable interrupts and return the previous interrupt priority level.
271 *
272 * @return Old interrupt priority level.
273 *
274 */
275_NO_TRACE static inline ipl_t interrupts_enable(void)
276{
277 ipl_t ipl = interrupts_read();
278
279 asm volatile ("sti\n");
280
281 return ipl;
282}
283
284/** Disable interrupts.
285 *
286 * Disable interrupts and return the previous interrupt priority level.
287 *
288 * @return Old interrupt priority level.
289 *
290 */
291_NO_TRACE static inline ipl_t interrupts_disable(void)
292{
293 ipl_t ipl = interrupts_read();
294
295 asm volatile ("cli\n");
296
297 return ipl;
298}
299
300/** Restore interrupt priority level.
301 *
302 * Restore a saved interrupt priority level.
303 *
304 * @param ipl Saved interrupt priority level.
305 *
306 */
307_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
308{
309 write_eflags((uint32_t) ipl);
310}
311
312/** Check interrupts state.
313 *
314 * @return True if interrupts are disabled.
315 *
316 */
317_NO_TRACE static inline bool interrupts_disabled(void)
318{
319 return ((read_eflags() & EFLAGS_IF) == 0);
320}
321
322#ifndef PROCESSOR_i486
323
324/** Write to MSR */
325_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
326{
327 asm volatile (
328 "wrmsr"
329 :: "c" (msr),
330 "a" ((uint32_t) (value)),
331 "d" ((uint32_t) (value >> 32))
332 );
333}
334
335_NO_TRACE static inline uint64_t read_msr(uint32_t msr)
336{
337 uint32_t ax, dx;
338
339 asm volatile (
340 "rdmsr"
341 : "=a" (ax),
342 "=d" (dx)
343 : "c" (msr)
344 );
345
346 return ((uint64_t) dx << 32) | ax;
347}
348
349#endif /* PROCESSOR_i486 */
350
351/** Invalidate TLB Entry.
352 *
353 * @param addr Address on a page whose TLB entry is to be invalidated.
354 *
355 */
356_NO_TRACE static inline void invlpg(uintptr_t addr)
357{
358 asm volatile (
359 "invlpg %[addr]\n"
360 :: [addr] "m" (*(sysarg_t *) addr)
361 );
362}
363
364/** Load GDTR register from memory.
365 *
366 * @param gdtr_reg Address of memory from where to load GDTR.
367 *
368 */
369_NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
370{
371 asm volatile (
372 "lgdtl %[gdtr_reg]\n"
373 :: [gdtr_reg] "m" (*gdtr_reg)
374 );
375}
376
377/** Store GDTR register to memory.
378 *
379 * @param gdtr_reg Address of memory to where to load GDTR.
380 *
381 */
382_NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
383{
384 asm volatile (
385 "sgdtl %[gdtr_reg]\n"
386 : [gdtr_reg] "=m" (*gdtr_reg)
387 );
388}
389
390/** Load IDTR register from memory.
391 *
392 * @param idtr_reg Address of memory from where to load IDTR.
393 *
394 */
395_NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
396{
397 asm volatile (
398 "lidtl %[idtr_reg]\n"
399 :: [idtr_reg] "m" (*idtr_reg)
400 );
401}
402
403/** Load TR from descriptor table.
404 *
405 * @param sel Selector specifying descriptor of TSS segment.
406 *
407 */
408_NO_TRACE static inline void tr_load(uint16_t sel)
409{
410 asm volatile (
411 "ltr %[sel]"
412 :: [sel] "r" (sel)
413 );
414}
415
416/** Load GS from descriptor table.
417 *
418 * @param sel Selector specifying descriptor of the GS segment.
419 *
420 */
421_NO_TRACE static inline void gs_load(uint16_t sel)
422{
423 asm volatile (
424 "mov %[sel], %%gs"
425 :: [sel] "r" (sel)
426 );
427}
428
429extern void paging_on(void);
430extern void enable_l_apic_in_msr(void);
431
432extern void asm_delay_loop(uint32_t);
433extern void asm_fake_loop(uint32_t);
434
435extern uintptr_t int_syscall;
436
437extern uintptr_t int_0;
438extern uintptr_t int_1;
439extern uintptr_t int_2;
440extern uintptr_t int_3;
441extern uintptr_t int_4;
442extern uintptr_t int_5;
443extern uintptr_t int_6;
444extern uintptr_t int_7;
445extern uintptr_t int_8;
446extern uintptr_t int_9;
447extern uintptr_t int_10;
448extern uintptr_t int_11;
449extern uintptr_t int_12;
450extern uintptr_t int_13;
451extern uintptr_t int_14;
452extern uintptr_t int_15;
453extern uintptr_t int_16;
454extern uintptr_t int_17;
455extern uintptr_t int_18;
456extern uintptr_t int_19;
457extern uintptr_t int_20;
458extern uintptr_t int_21;
459extern uintptr_t int_22;
460extern uintptr_t int_23;
461extern uintptr_t int_24;
462extern uintptr_t int_25;
463extern uintptr_t int_26;
464extern uintptr_t int_27;
465extern uintptr_t int_28;
466extern uintptr_t int_29;
467extern uintptr_t int_30;
468extern uintptr_t int_31;
469extern uintptr_t int_32;
470extern uintptr_t int_33;
471extern uintptr_t int_34;
472extern uintptr_t int_35;
473extern uintptr_t int_36;
474extern uintptr_t int_37;
475extern uintptr_t int_38;
476extern uintptr_t int_39;
477extern uintptr_t int_40;
478extern uintptr_t int_41;
479extern uintptr_t int_42;
480extern uintptr_t int_43;
481extern uintptr_t int_44;
482extern uintptr_t int_45;
483extern uintptr_t int_46;
484extern uintptr_t int_47;
485extern uintptr_t int_48;
486extern uintptr_t int_49;
487extern uintptr_t int_50;
488extern uintptr_t int_51;
489extern uintptr_t int_52;
490extern uintptr_t int_53;
491extern uintptr_t int_54;
492extern uintptr_t int_55;
493extern uintptr_t int_56;
494extern uintptr_t int_57;
495extern uintptr_t int_58;
496extern uintptr_t int_59;
497extern uintptr_t int_60;
498extern uintptr_t int_61;
499extern uintptr_t int_62;
500extern uintptr_t int_63;
501
502#endif
503
504/** @}
505 */
Note: See TracBrowser for help on using the repository browser.