[84176f3] | 1 | /*
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| 2 | * Copyright (c) 2015 Petr Pavlu
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup kernel_arm64
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Interrupts controlling routines.
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| 34 | */
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| 35 |
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| 36 | #include <arch/interrupt.h>
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| 37 | #include <arch/machine_func.h>
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| 38 | #include <ddi/irq.h>
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| 39 | #include <interrupt.h>
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| 40 | #include <time/clock.h>
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| 41 |
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| 42 | static irq_t timer_irq;
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| 43 | static uint64_t timer_increment;
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| 44 |
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| 45 | /** Disable interrupts.
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| 46 | *
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| 47 | * @return Old interrupt priority level.
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| 48 | */
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| 49 | ipl_t interrupts_disable(void)
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| 50 | {
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| 51 | uint64_t daif = DAIF_read();
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| 52 |
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| 53 | DAIF_write(daif | DAIF_IRQ_FLAG);
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| 54 |
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[6de65f3] | 55 | return daif & DAIF_IRQ_FLAG;
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[84176f3] | 56 | }
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| 57 |
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| 58 | /** Enable interrupts.
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| 59 | *
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| 60 | * @return Old interrupt priority level.
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| 61 | */
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| 62 | ipl_t interrupts_enable(void)
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| 63 | {
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| 64 | uint64_t daif = DAIF_read();
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| 65 |
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| 66 | DAIF_write(daif & ~DAIF_IRQ_FLAG);
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| 67 |
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[6de65f3] | 68 | return daif & DAIF_IRQ_FLAG;
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[84176f3] | 69 | }
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| 70 |
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| 71 | /** Restore interrupt priority level.
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| 72 | *
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| 73 | * @param ipl Saved interrupt priority level.
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| 74 | */
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| 75 | void interrupts_restore(ipl_t ipl)
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| 76 | {
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| 77 | uint64_t daif = DAIF_read();
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| 78 |
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[6de65f3] | 79 | DAIF_write((daif & ~DAIF_IRQ_FLAG) | (ipl & DAIF_IRQ_FLAG));
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[84176f3] | 80 | }
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| 81 |
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| 82 | /** Read interrupt priority level.
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| 83 | *
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| 84 | * @return Current interrupt priority level.
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| 85 | */
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| 86 | ipl_t interrupts_read(void)
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| 87 | {
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[6de65f3] | 88 | return DAIF_read() & DAIF_IRQ_FLAG;
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[84176f3] | 89 | }
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| 90 |
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| 91 | /** Check interrupts state.
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| 92 | *
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| 93 | * @return True if interrupts are disabled.
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| 94 | */
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| 95 | bool interrupts_disabled(void)
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| 96 | {
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| 97 | return DAIF_read() & DAIF_IRQ_FLAG;
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| 98 | }
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| 99 |
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| 100 | /** Suspend the virtual timer. */
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| 101 | static void timer_suspend(void)
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| 102 | {
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| 103 | uint64_t cntv_ctl = CNTV_CTL_EL0_read();
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| 104 |
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| 105 | CNTV_CTL_EL0_write(cntv_ctl | CNTV_CTL_IMASK_FLAG);
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| 106 | }
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| 107 |
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| 108 | /** Start the virtual timer. */
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| 109 | static void timer_start(void)
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| 110 | {
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| 111 | uint64_t cntfrq = CNTFRQ_EL0_read();
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| 112 | uint64_t cntvct = CNTVCT_EL0_read();
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| 113 | uint64_t cntv_ctl = CNTV_CTL_EL0_read();
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| 114 |
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| 115 | /* Calculate the increment. */
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| 116 | timer_increment = cntfrq / HZ;
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| 117 |
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| 118 | /* Program the timer. */
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| 119 | CNTV_CVAL_EL0_write(cntvct + timer_increment);
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| 120 | CNTV_CTL_EL0_write(
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| 121 | (cntv_ctl & ~CNTV_CTL_IMASK_FLAG) | CNTV_CTL_ENABLE_FLAG);
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| 122 | }
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| 123 |
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| 124 | /** Claim the virtual timer interrupt. */
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| 125 | static irq_ownership_t timer_claim(irq_t *irq)
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| 126 | {
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| 127 | return IRQ_ACCEPT;
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| 128 | }
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| 129 |
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| 130 | /** Handle the virtual timer interrupt. */
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| 131 | static void timer_irq_handler(irq_t *irq)
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| 132 | {
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| 133 | uint64_t cntvct = CNTVCT_EL0_read();
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| 134 | uint64_t cntv_cval = CNTV_CVAL_EL0_read();
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| 135 |
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| 136 | uint64_t drift = cntvct - cntv_cval;
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| 137 | while (drift > timer_increment) {
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| 138 | drift -= timer_increment;
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[4760793] | 139 | CPU_LOCAL->missed_clock_ticks++;
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[84176f3] | 140 | }
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| 141 | CNTV_CVAL_EL0_write(cntvct + timer_increment - drift);
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| 142 |
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| 143 | /*
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| 144 | * We are holding a lock which prevents preemption.
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| 145 | * Release the lock, call clock() and reacquire the lock again.
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| 146 | */
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| 147 | irq_spinlock_unlock(&irq->lock, false);
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| 148 | clock();
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| 149 | irq_spinlock_lock(&irq->lock, false);
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| 150 | }
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| 151 |
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| 152 | /** Initialize basic tables for exception dispatching. */
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| 153 | void interrupt_init(void)
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| 154 | {
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| 155 | size_t irq_count = machine_get_irq_count();
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| 156 | irq_init(irq_count, irq_count);
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| 157 |
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| 158 | /* Initialize virtual timer. */
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| 159 | timer_suspend();
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| 160 | inr_t timer_inr = machine_enable_vtimer_irq();
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| 161 |
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| 162 | irq_initialize(&timer_irq);
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| 163 | timer_irq.inr = timer_inr;
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| 164 | timer_irq.claim = timer_claim;
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| 165 | timer_irq.handler = timer_irq_handler;
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| 166 | irq_register(&timer_irq);
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| 167 |
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| 168 | timer_start();
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| 169 | }
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| 170 |
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| 171 | /** @}
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| 172 | */
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