source: mainline/kernel/arch/arm64/src/asm.S@ f14a900

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f14a900 was 28a5ebd, checked in by Martin Decky <martin@…>, 6 years ago

Use char32_t instead of wchat_t to represent UTF-32 strings

The intention of the native HelenOS string API has been always to
support Unicode in the UTF-8 and UTF-32 encodings as the sole character
representations and ignore the obsolete mess of older single-byte and
multibyte character encodings. Before C11, the wchar_t type has been
slightly misused for the purpose of the UTF-32 strings. The newer
char32_t type is obviously a much more suitable option. The standard
defines char32_t as uint_least32_t, thus we can take the liberty to fix
it to uint32_t.

To maintain compatilibity with the C Standard, the putwchar(wchar_t)
functions has been replaced by our custom putuchar(char32_t) functions
where appropriate.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 * Copyright (c) 2015 Petr Pavlu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <abi/asmtool.h>
30#include <arch/exception.h>
31#include <arch/istate_struct.h>
32
33.text
34
35FUNCTION_BEGIN(memcpy_from_uspace)
36FUNCTION_BEGIN(memcpy_to_uspace)
37 /* Simple (un-optimized) memcpy(). */
38 cbz x2, 2f
39 mov x3, x0
401:
41 ldrb w4, [x1], #1
42 strb w4, [x3], #1
43 subs x2, x2, #1
44 b.ne 1b
45
462:
47 ret
48FUNCTION_END(memcpy_from_uspace)
49FUNCTION_END(memcpy_to_uspace)
50
51FUNCTION_BEGIN(memcpy_from_uspace_failover_address)
52FUNCTION_BEGIN(memcpy_to_uspace_failover_address)
53 mov x0, #0
54 ret
55FUNCTION_END(memcpy_from_uspace_failover_address)
56FUNCTION_END(memcpy_to_uspace_failover_address)
57
58FUNCTION_BEGIN(early_putuchar)
59 ret
60FUNCTION_END(early_putuchar)
61
62/* Static checks for the istate_t save/load. */
63#if ISTATE_OFFSET_X0 + 8 != ISTATE_OFFSET_X1
64#error x0 and x1 are not successive in istate_t
65#endif
66#if ISTATE_OFFSET_X2 + 8 != ISTATE_OFFSET_X3
67#error x2 and x3 are not successive in istate_t
68#endif
69#if ISTATE_OFFSET_X4 + 8 != ISTATE_OFFSET_X5
70#error x4 and x5 are not successive in istate_t
71#endif
72#if ISTATE_OFFSET_X6 + 8 != ISTATE_OFFSET_X7
73#error x6 and x7 are not successive in istate_t
74#endif
75#if ISTATE_OFFSET_X8 + 8 != ISTATE_OFFSET_X9
76#error x8 and x9 are not successive in istate_t
77#endif
78#if ISTATE_OFFSET_X10 + 8 != ISTATE_OFFSET_X11
79#error x10 and x11 are not successive in istate_t
80#endif
81#if ISTATE_OFFSET_X12 + 8 != ISTATE_OFFSET_X13
82#error x12 and x13 are not successive in istate_t
83#endif
84#if ISTATE_OFFSET_X14 + 8 != ISTATE_OFFSET_X15
85#error x14 and x15 are not successive in istate_t
86#endif
87#if ISTATE_OFFSET_X16 + 8 != ISTATE_OFFSET_X17
88#error x16 and x17 are not successive in istate_t
89#endif
90#if ISTATE_OFFSET_X18 + 8 != ISTATE_OFFSET_X19
91#error x18 and x19 are not successive in istate_t
92#endif
93#if ISTATE_OFFSET_X20 + 8 != ISTATE_OFFSET_X21
94#error x20 and x21 are not successive in istate_t
95#endif
96#if ISTATE_OFFSET_X22 + 8 != ISTATE_OFFSET_X23
97#error x22 and x23 are not successive in istate_t
98#endif
99#if ISTATE_OFFSET_X24 + 8 != ISTATE_OFFSET_X25
100#error x24 and x25 are not successive in istate_t
101#endif
102#if ISTATE_OFFSET_X26 + 8 != ISTATE_OFFSET_X27
103#error x26 and x27 are not successive in istate_t
104#endif
105#if ISTATE_OFFSET_X28 + 8 != ISTATE_OFFSET_X29
106#error x28 and x29 are not successive in istate_t
107#endif
108#if ISTATE_OFFSET_SPSR + 8 != ISTATE_OFFSET_SP
109#error spsr and sp are not successive in istate_t
110#endif
111#if ISTATE_OFFSET_PC + 8 != ISTATE_OFFSET_TPIDR
112#error pc and tpidr are not successive in istate_t
113#endif
114
115/* Exception vector. */
116.macro handler i
117handler_\i:
118 /*
119 * Initial code for each handler, at maximum 128 bytes (32
120 * instructions).
121 */
122
123 /* Save current state. */
124 sub sp, sp, #ISTATE_SIZE /* 0x00 */
125 stp x0, x1, [sp, #ISTATE_OFFSET_X0] /* 0x04 */
126 stp x2, x3, [sp, #ISTATE_OFFSET_X2] /* 0x08 */
127 stp x4, x5, [sp, #ISTATE_OFFSET_X4] /* 0x0c */
128 stp x6, x7, [sp, #ISTATE_OFFSET_X6] /* 0x10 */
129 stp x8, x9, [sp, #ISTATE_OFFSET_X8] /* 0x14 */
130 stp x10, x11, [sp, #ISTATE_OFFSET_X10] /* 0x18 */
131 stp x12, x13, [sp, #ISTATE_OFFSET_X12] /* 0x1c */
132 stp x14, x15, [sp, #ISTATE_OFFSET_X14] /* 0x20 */
133 stp x16, x17, [sp, #ISTATE_OFFSET_X16] /* 0x24 */
134 stp x18, x19, [sp, #ISTATE_OFFSET_X18] /* 0x28 */
135 stp x20, x21, [sp, #ISTATE_OFFSET_X20] /* 0x2c */
136 stp x22, x23, [sp, #ISTATE_OFFSET_X22] /* 0x30 */
137 stp x24, x25, [sp, #ISTATE_OFFSET_X24] /* 0x34 */
138 stp x26, x27, [sp, #ISTATE_OFFSET_X26] /* 0x38 */
139 stp x28, x29, [sp, #ISTATE_OFFSET_X28] /* 0x3c */
140 str x30, [sp, #ISTATE_OFFSET_X30] /* 0x40 */
141
142 mrs x0, spsr_el1 /* 0x44 */
143 mrs x1, sp_el0 /* 0x48 */
144 stp x0, x1, [sp, #ISTATE_OFFSET_SPSR] /* 0x4c */
145
146 mrs x0, elr_el1 /* 0x50 */
147 mrs x1, tpidr_el0 /* 0x54 */
148 stp x0, x1, [sp, #ISTATE_OFFSET_PC] /* 0x58 */
149
150 mov x0, #\i /* 0x5c */
151 mov x1, sp /* 0x60 */
152 bl exc_dispatch /* 0x64 */
153
154 /* Restore previous state. */
155 ldp x0, x1, [sp, #ISTATE_OFFSET_SPSR] /* 0x68 */
156 msr spsr_el1, x0 /* 0x6c */
157 msr sp_el0, x1 /* 0x70 */
158
159 ldp x0, x1, [sp, #ISTATE_OFFSET_PC] /* 0x74 */
160 msr elr_el1, x0 /* 0x78 */
161 b exc_restore_end /* 0x7c */
162.endm
163
164exc_restore_end:
165 /* Restore remaining registers and return from the exception handler. */
166 msr tpidr_el0, x1
167 ldp x0, x1, [sp, #ISTATE_OFFSET_X0]
168 ldp x2, x3, [sp, #ISTATE_OFFSET_X2]
169 ldp x4, x5, [sp, #ISTATE_OFFSET_X4]
170 ldp x6, x7, [sp, #ISTATE_OFFSET_X6]
171 ldp x8, x9, [sp, #ISTATE_OFFSET_X8]
172 ldp x10, x11, [sp, #ISTATE_OFFSET_X10]
173 ldp x12, x13, [sp, #ISTATE_OFFSET_X12]
174 ldp x14, x15, [sp, #ISTATE_OFFSET_X14]
175 ldp x16, x17, [sp, #ISTATE_OFFSET_X16]
176 ldp x18, x19, [sp, #ISTATE_OFFSET_X18]
177 ldp x20, x21, [sp, #ISTATE_OFFSET_X20]
178 ldp x22, x23, [sp, #ISTATE_OFFSET_X22]
179 ldp x24, x25, [sp, #ISTATE_OFFSET_X24]
180 ldp x26, x27, [sp, #ISTATE_OFFSET_X26]
181 ldp x28, x29, [sp, #ISTATE_OFFSET_X28]
182 ldr x30, [sp, #ISTATE_OFFSET_X30]
183 add sp, sp, #ISTATE_SIZE
184 eret
185
186.align 11
187SYMBOL(exc_vector)
188.org exc_vector + 0x000
189 handler EXC_CURRENT_EL_SP_SEL0_SYNCH
190.org exc_vector + 0x080
191 handler EXC_CURRENT_EL_SP_SEL0_IRQ
192.org exc_vector + 0x100
193 handler EXC_CURRENT_EL_SP_SEL0_FIQ
194.org exc_vector + 0x180
195 handler EXC_CURRENT_EL_SP_SEL0_SERROR
196.org exc_vector + 0x200
197 handler EXC_CURRENT_EL_SP_SELX_SYNCH
198.org exc_vector + 0x280
199 handler EXC_CURRENT_EL_SP_SELX_IRQ
200.org exc_vector + 0x300
201 handler EXC_CURRENT_EL_SP_SELX_FIQ
202.org exc_vector + 0x380
203 handler EXC_CURRENT_EL_SP_SELX_SERROR
204.org exc_vector + 0x400
205 handler EXC_LOWER_EL_AARCH64_SYNCH
206.org exc_vector + 0x480
207 handler EXC_LOWER_EL_AARCH64_IRQ
208.org exc_vector + 0x500
209 handler EXC_LOWER_EL_AARCH64_FIQ
210.org exc_vector + 0x580
211 handler EXC_LOWER_EL_AARCH64_SERROR
212.org exc_vector + 0x600
213 handler EXC_LOWER_EL_AARCH32_SYNCH
214.org exc_vector + 0x680
215 handler EXC_LOWER_EL_AARCH32_IRQ
216.org exc_vector + 0x700
217 handler EXC_LOWER_EL_AARCH32_FIQ
218.org exc_vector + 0x780
219 handler EXC_LOWER_EL_AARCH32_SERROR
220.org exc_vector + 0x800
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