| [84176f3] | 1 | /*
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| 2 | * Copyright (c) 2015 Petr Pavlu
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <abi/asmtool.h>
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| 30 | #include <arch/exception.h>
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| 31 | #include <arch/istate_struct.h>
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| 32 |
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| 33 | .text
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| 34 |
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| 35 | FUNCTION_BEGIN(memcpy_from_uspace)
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| 36 | FUNCTION_BEGIN(memcpy_to_uspace)
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| 37 | /* Simple (un-optimized) memcpy(). */
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| 38 | cbz x2, 2f
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| 39 | mov x3, x0
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| 40 | 1:
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| 41 | ldrb w4, [x1], #1
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| 42 | strb w4, [x3], #1
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| 43 | subs x2, x2, #1
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| 44 | b.ne 1b
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| 45 |
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| 46 | 2:
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| 47 | ret
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| 48 | FUNCTION_END(memcpy_from_uspace)
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| 49 | FUNCTION_END(memcpy_to_uspace)
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| 50 |
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| 51 | FUNCTION_BEGIN(memcpy_from_uspace_failover_address)
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| 52 | FUNCTION_BEGIN(memcpy_to_uspace_failover_address)
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| 53 | mov x0, #0
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| 54 | ret
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| 55 | FUNCTION_END(memcpy_from_uspace_failover_address)
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| 56 | FUNCTION_END(memcpy_to_uspace_failover_address)
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| 57 |
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| [06f10ac] | 58 | /** Flush instruction caches
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| 59 | *
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| 60 | * @param x0 Starting address of the flushing.
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| 61 | * @param x1 Number of bytes to flush.
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| 62 | *
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| 63 | */
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| 64 | FUNCTION_BEGIN(smc_coherence)
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| 65 | /* Initialize loop */
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| 66 | mov x9, x0
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| 67 | mov x10, xzr
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| 68 |
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| 69 | __dc_loop:
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| 70 | /* Data or Unified Cache Line Clean */
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| 71 | dc cvau, x9
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| 72 | add x9, x9, #4
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| 73 | add x10, x10, #4
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| 74 | cmp x10, x1
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| 75 | blo __dc_loop
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| 76 |
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| 77 | dsb ish
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| 78 |
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| 79 | /* Initialize loop */
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| 80 | mov x9, x0
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| 81 | mov x10, xzr
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| 82 |
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| 83 | __ic_loop:
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| 84 | /* Instruction Cache Line Invalidate */
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| 85 | ic ivau, x9
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| 86 | add x9, x9, #4
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| 87 | add x10, x10, #4
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| 88 | cmp x10, x1
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| 89 | blo __ic_loop
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| 90 |
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| 91 | dsb ish
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| 92 | isb
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| 93 | ret
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| 94 | FUNCTION_END(smc_coherence)
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| 95 |
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| [84176f3] | 96 | /* Static checks for the istate_t save/load. */
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| 97 | #if ISTATE_OFFSET_X0 + 8 != ISTATE_OFFSET_X1
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| 98 | #error x0 and x1 are not successive in istate_t
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| 99 | #endif
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| 100 | #if ISTATE_OFFSET_X2 + 8 != ISTATE_OFFSET_X3
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| 101 | #error x2 and x3 are not successive in istate_t
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| 102 | #endif
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| 103 | #if ISTATE_OFFSET_X4 + 8 != ISTATE_OFFSET_X5
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| 104 | #error x4 and x5 are not successive in istate_t
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| 105 | #endif
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| 106 | #if ISTATE_OFFSET_X6 + 8 != ISTATE_OFFSET_X7
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| 107 | #error x6 and x7 are not successive in istate_t
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| 108 | #endif
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| 109 | #if ISTATE_OFFSET_X8 + 8 != ISTATE_OFFSET_X9
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| 110 | #error x8 and x9 are not successive in istate_t
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| 111 | #endif
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| 112 | #if ISTATE_OFFSET_X10 + 8 != ISTATE_OFFSET_X11
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| 113 | #error x10 and x11 are not successive in istate_t
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| 114 | #endif
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| 115 | #if ISTATE_OFFSET_X12 + 8 != ISTATE_OFFSET_X13
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| 116 | #error x12 and x13 are not successive in istate_t
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| 117 | #endif
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| 118 | #if ISTATE_OFFSET_X14 + 8 != ISTATE_OFFSET_X15
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| 119 | #error x14 and x15 are not successive in istate_t
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| 120 | #endif
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| 121 | #if ISTATE_OFFSET_X16 + 8 != ISTATE_OFFSET_X17
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| 122 | #error x16 and x17 are not successive in istate_t
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| 123 | #endif
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| 124 | #if ISTATE_OFFSET_X18 + 8 != ISTATE_OFFSET_X19
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| 125 | #error x18 and x19 are not successive in istate_t
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| 126 | #endif
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| 127 | #if ISTATE_OFFSET_X20 + 8 != ISTATE_OFFSET_X21
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| 128 | #error x20 and x21 are not successive in istate_t
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| 129 | #endif
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| 130 | #if ISTATE_OFFSET_X22 + 8 != ISTATE_OFFSET_X23
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| 131 | #error x22 and x23 are not successive in istate_t
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| 132 | #endif
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| 133 | #if ISTATE_OFFSET_X24 + 8 != ISTATE_OFFSET_X25
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| 134 | #error x24 and x25 are not successive in istate_t
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| 135 | #endif
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| 136 | #if ISTATE_OFFSET_X26 + 8 != ISTATE_OFFSET_X27
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| 137 | #error x26 and x27 are not successive in istate_t
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| 138 | #endif
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| 139 | #if ISTATE_OFFSET_X28 + 8 != ISTATE_OFFSET_X29
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| 140 | #error x28 and x29 are not successive in istate_t
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| 141 | #endif
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| 142 | #if ISTATE_OFFSET_SPSR + 8 != ISTATE_OFFSET_SP
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| 143 | #error spsr and sp are not successive in istate_t
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| 144 | #endif
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| 145 | #if ISTATE_OFFSET_PC + 8 != ISTATE_OFFSET_TPIDR
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| 146 | #error pc and tpidr are not successive in istate_t
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| 147 | #endif
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| 148 |
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| 149 | /* Exception vector. */
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| 150 | .macro handler i
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| 151 | handler_\i:
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| 152 | /*
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| 153 | * Initial code for each handler, at maximum 128 bytes (32
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| 154 | * instructions).
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| 155 | */
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| 156 |
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| 157 | /* Save current state. */
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| 158 | sub sp, sp, #ISTATE_SIZE /* 0x00 */
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| 159 | stp x0, x1, [sp, #ISTATE_OFFSET_X0] /* 0x04 */
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| 160 | stp x2, x3, [sp, #ISTATE_OFFSET_X2] /* 0x08 */
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| 161 | stp x4, x5, [sp, #ISTATE_OFFSET_X4] /* 0x0c */
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| 162 | stp x6, x7, [sp, #ISTATE_OFFSET_X6] /* 0x10 */
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| 163 | stp x8, x9, [sp, #ISTATE_OFFSET_X8] /* 0x14 */
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| 164 | stp x10, x11, [sp, #ISTATE_OFFSET_X10] /* 0x18 */
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| 165 | stp x12, x13, [sp, #ISTATE_OFFSET_X12] /* 0x1c */
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| 166 | stp x14, x15, [sp, #ISTATE_OFFSET_X14] /* 0x20 */
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| 167 | stp x16, x17, [sp, #ISTATE_OFFSET_X16] /* 0x24 */
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| 168 | stp x18, x19, [sp, #ISTATE_OFFSET_X18] /* 0x28 */
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| 169 | stp x20, x21, [sp, #ISTATE_OFFSET_X20] /* 0x2c */
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| 170 | stp x22, x23, [sp, #ISTATE_OFFSET_X22] /* 0x30 */
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| 171 | stp x24, x25, [sp, #ISTATE_OFFSET_X24] /* 0x34 */
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| 172 | stp x26, x27, [sp, #ISTATE_OFFSET_X26] /* 0x38 */
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| 173 | stp x28, x29, [sp, #ISTATE_OFFSET_X28] /* 0x3c */
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| 174 | str x30, [sp, #ISTATE_OFFSET_X30] /* 0x40 */
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| 175 |
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| 176 | mrs x0, spsr_el1 /* 0x44 */
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| 177 | mrs x1, sp_el0 /* 0x48 */
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| 178 | stp x0, x1, [sp, #ISTATE_OFFSET_SPSR] /* 0x4c */
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| 179 |
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| 180 | mrs x0, elr_el1 /* 0x50 */
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| 181 | mrs x1, tpidr_el0 /* 0x54 */
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| 182 | stp x0, x1, [sp, #ISTATE_OFFSET_PC] /* 0x58 */
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| 183 |
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| 184 | mov x0, #\i /* 0x5c */
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| 185 | mov x1, sp /* 0x60 */
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| 186 | bl exc_dispatch /* 0x64 */
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| 187 |
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| 188 | /* Restore previous state. */
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| 189 | ldp x0, x1, [sp, #ISTATE_OFFSET_SPSR] /* 0x68 */
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| 190 | msr spsr_el1, x0 /* 0x6c */
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| 191 | msr sp_el0, x1 /* 0x70 */
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| 192 |
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| 193 | ldp x0, x1, [sp, #ISTATE_OFFSET_PC] /* 0x74 */
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| 194 | msr elr_el1, x0 /* 0x78 */
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| 195 | b exc_restore_end /* 0x7c */
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| 196 | .endm
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| 197 |
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| 198 | exc_restore_end:
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| 199 | /* Restore remaining registers and return from the exception handler. */
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| 200 | msr tpidr_el0, x1
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| 201 | ldp x0, x1, [sp, #ISTATE_OFFSET_X0]
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| 202 | ldp x2, x3, [sp, #ISTATE_OFFSET_X2]
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| 203 | ldp x4, x5, [sp, #ISTATE_OFFSET_X4]
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| 204 | ldp x6, x7, [sp, #ISTATE_OFFSET_X6]
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| 205 | ldp x8, x9, [sp, #ISTATE_OFFSET_X8]
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| 206 | ldp x10, x11, [sp, #ISTATE_OFFSET_X10]
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| 207 | ldp x12, x13, [sp, #ISTATE_OFFSET_X12]
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| 208 | ldp x14, x15, [sp, #ISTATE_OFFSET_X14]
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| 209 | ldp x16, x17, [sp, #ISTATE_OFFSET_X16]
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| 210 | ldp x18, x19, [sp, #ISTATE_OFFSET_X18]
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| 211 | ldp x20, x21, [sp, #ISTATE_OFFSET_X20]
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| 212 | ldp x22, x23, [sp, #ISTATE_OFFSET_X22]
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| 213 | ldp x24, x25, [sp, #ISTATE_OFFSET_X24]
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| 214 | ldp x26, x27, [sp, #ISTATE_OFFSET_X26]
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| 215 | ldp x28, x29, [sp, #ISTATE_OFFSET_X28]
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| 216 | ldr x30, [sp, #ISTATE_OFFSET_X30]
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| 217 | add sp, sp, #ISTATE_SIZE
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| 218 | eret
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| 219 |
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| 220 | .align 11
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| 221 | SYMBOL(exc_vector)
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| 222 | .org exc_vector + 0x000
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| 223 | handler EXC_CURRENT_EL_SP_SEL0_SYNCH
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| 224 | .org exc_vector + 0x080
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| 225 | handler EXC_CURRENT_EL_SP_SEL0_IRQ
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| 226 | .org exc_vector + 0x100
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| 227 | handler EXC_CURRENT_EL_SP_SEL0_FIQ
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| 228 | .org exc_vector + 0x180
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| 229 | handler EXC_CURRENT_EL_SP_SEL0_SERROR
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| 230 | .org exc_vector + 0x200
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| 231 | handler EXC_CURRENT_EL_SP_SELX_SYNCH
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| 232 | .org exc_vector + 0x280
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| 233 | handler EXC_CURRENT_EL_SP_SELX_IRQ
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| 234 | .org exc_vector + 0x300
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| 235 | handler EXC_CURRENT_EL_SP_SELX_FIQ
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| 236 | .org exc_vector + 0x380
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| 237 | handler EXC_CURRENT_EL_SP_SELX_SERROR
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| 238 | .org exc_vector + 0x400
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| 239 | handler EXC_LOWER_EL_AARCH64_SYNCH
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| 240 | .org exc_vector + 0x480
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| 241 | handler EXC_LOWER_EL_AARCH64_IRQ
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| 242 | .org exc_vector + 0x500
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| 243 | handler EXC_LOWER_EL_AARCH64_FIQ
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| 244 | .org exc_vector + 0x580
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| 245 | handler EXC_LOWER_EL_AARCH64_SERROR
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| 246 | .org exc_vector + 0x600
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| 247 | handler EXC_LOWER_EL_AARCH32_SYNCH
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| 248 | .org exc_vector + 0x680
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| 249 | handler EXC_LOWER_EL_AARCH32_IRQ
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| 250 | .org exc_vector + 0x700
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| 251 | handler EXC_LOWER_EL_AARCH32_FIQ
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| 252 | .org exc_vector + 0x780
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| 253 | handler EXC_LOWER_EL_AARCH32_SERROR
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| 254 | .org exc_vector + 0x800
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