source: mainline/kernel/arch/arm32/src/start.S@ afd0106

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since afd0106 was 6ac14a70, checked in by Vineeth Pillai <vineethrp@…>, 16 years ago

ARM port for development board integratorcp(ARM926EJ core module).

  • Property mode set to 100644
File size: 2.1 KB
Line 
1#
2# Copyright (c) 2007 Michal Kebrt
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/asm/boot.h>
30
31.text
32
33.global kernel_image_start
34.global exc_stack
35.global supervisor_sp
36
37kernel_image_start:
38
39 # initialize Stack pointer for exception modes
40 mrs r4, cpsr
41 bic r4, r4, #0x1f
42
43 #FIQ Mode
44 orr r3, r4, #0x11
45 msr cpsr_c, r3
46 ldr sp, =exc_stack
47
48 #IRQ Mode
49 orr r3, r4, #0x12
50 msr cpsr_c, r3
51 ldr sp, =exc_stack
52
53 #ABORT Mode
54 orr r3, r4, #0x17
55 msr cpsr_c, r3
56 ldr sp, =exc_stack
57
58 #UNDEFINED Mode
59 orr r3, r4, #0x1b
60 msr cpsr_c, r3
61 ldr sp, =exc_stack
62
63 # switch to supervisor mode
64 orr r3, r4, #0x13
65 msr cpsr_c, r3
66
67 ldr sp, =temp_stack
68
69 bl arch_pre_main
70
71 bl main_bsp
72
73 .space TEMP_STACK_SIZE
74temp_stack:
75
76 .space 1024
77exc_stack:
78
79supervisor_sp:
80 .space 4
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