source: mainline/kernel/arch/arm32/src/mach/integratorcp/integratorcp.c@ dfeb4e2

Last change on this file since dfeb4e2 was 24abb85d, checked in by Jakub Jermar <jakub@…>, 8 years ago

Remove SYS_DEVICE_ASSIGN_DEVNO
  • Property mode set to 100644
File size: 9.5 KB
Line 
1/*
2 * Copyright (c) 2009 Vineeth Pillai
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32integratorcp
30 * @{
31 */
32/** @file
33 * @brief ICP drivers.
34 */
35
36#include <interrupt.h>
37#include <ipc/irq.h>
38#include <console/chardev.h>
39#include <genarch/drivers/pl011/pl011.h>
40#include <genarch/drivers/pl050/pl050.h>
41#include <genarch/kbrd/kbrd.h>
42#include <genarch/srln/srln.h>
43#include <console/console.h>
44#include <sysinfo/sysinfo.h>
45#include <mm/page.h>
46#include <mm/frame.h>
47#include <mm/km.h>
48#include <arch/mm/frame.h>
49#include <arch/mach/integratorcp/integratorcp.h>
50#include <genarch/fb/fb.h>
51#include <abi/fb/visuals.h>
52#include <ddi/ddi.h>
53#include <log.h>
54
55
56#define SDRAM_SIZE \
57 sdram[(*(uint32_t *) (ICP_CMCR + ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2]
58
59static struct {
60 icp_hw_map_t hw_map;
61 irq_t timer_irq;
62 pl011_uart_t uart;
63} icp;
64
65struct arm_machine_ops icp_machine_ops = {
66 icp_init,
67 icp_timer_irq_start,
68 icp_cpu_halt,
69 icp_get_memory_extents,
70 icp_irq_exception,
71 icp_frame_init,
72 icp_output_init,
73 icp_input_init,
74 icp_get_irq_count,
75 icp_get_platform_name
76};
77
78static bool hw_map_init_called = false;
79uint32_t sdram[8] = {
80 16777216, /* 16mb */
81 33554432, /* 32mb */
82 67108864, /* 64mb */
83 134217728, /* 128mb */
84 268435456, /* 256mb */
85 0, /* Reserverd */
86 0, /* Reserverd */
87 0 /* Reserverd */
88 };
89
90void icp_vga_init(void);
91
92/** Initializes the vga
93 *
94 */
95void icp_vga_init(void)
96{
97 *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0x14) = 0xA05F0000;
98 *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0x1C) = 0x12C11000;
99 *(uint32_t *) icp.hw_map.vga = 0x3F1F3F9C;
100 *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x4) = 0x080B61DF;
101 *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x8) = 0x067F3800;
102 *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x10) = ICP_FB;
103 *(uint32_t *) ((char *)(icp.hw_map.vga) + 0x1C) = 0x182B;
104 *(uint32_t *) ((char *)(icp.hw_map.cmcr) + 0xC) = 0x33805000;
105
106}
107
108/** Returns the mask of active interrupts. */
109static inline uint32_t icp_irqc_get_sources(void)
110{
111 return *((uint32_t *) icp.hw_map.irqc);
112}
113
114/** Masks interrupt.
115 *
116 * @param irq interrupt number
117 */
118static inline void icp_irqc_mask(uint32_t irq)
119{
120 *((uint32_t *) icp.hw_map.irqc_mask) = (1 << irq);
121}
122
123
124/** Unmasks interrupt.
125 *
126 * @param irq interrupt number
127 */
128static inline void icp_irqc_unmask(uint32_t irq)
129{
130 *((uint32_t *) icp.hw_map.irqc_unmask) |= (1 << irq);
131}
132
133/** Initializes icp.hw_map. */
134void icp_init(void)
135{
136 icp.hw_map.uart = km_map(ICP_UART, PAGE_SIZE,
137 PAGE_WRITE | PAGE_NOT_CACHEABLE);
138 icp.hw_map.kbd_ctrl = km_map(ICP_KBD, PAGE_SIZE, PAGE_NOT_CACHEABLE);
139 icp.hw_map.kbd_stat = icp.hw_map.kbd_ctrl + ICP_KBD_STAT;
140 icp.hw_map.kbd_data = icp.hw_map.kbd_ctrl + ICP_KBD_DATA;
141 icp.hw_map.kbd_intstat = icp.hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
142 icp.hw_map.rtc = km_map(ICP_RTC, PAGE_SIZE,
143 PAGE_WRITE | PAGE_NOT_CACHEABLE);
144 icp.hw_map.rtc1_load = icp.hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
145 icp.hw_map.rtc1_read = icp.hw_map.rtc + ICP_RTC1_READ_OFFSET;
146 icp.hw_map.rtc1_ctl = icp.hw_map.rtc + ICP_RTC1_CTL_OFFSET;
147 icp.hw_map.rtc1_intrclr = icp.hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;
148 icp.hw_map.rtc1_bgload = icp.hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;
149 icp.hw_map.rtc1_intrstat = icp.hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
150
151 icp.hw_map.irqc = km_map(ICP_IRQC, PAGE_SIZE,
152 PAGE_WRITE | PAGE_NOT_CACHEABLE);
153 icp.hw_map.irqc_mask = icp.hw_map.irqc + ICP_IRQC_MASK_OFFSET;
154 icp.hw_map.irqc_unmask = icp.hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
155 icp.hw_map.cmcr = km_map(ICP_CMCR, PAGE_SIZE,
156 PAGE_WRITE | PAGE_NOT_CACHEABLE);
157 icp.hw_map.sdramcr = icp.hw_map.cmcr + ICP_SDRAMCR_OFFSET;
158 icp.hw_map.vga = km_map(ICP_VGA, PAGE_SIZE,
159 PAGE_WRITE | PAGE_NOT_CACHEABLE);
160
161 hw_map_init_called = true;
162}
163
164/** Starts icp Real Time Clock device, which asserts regular interrupts.
165 *
166 * @param frequency Interrupts frequency (0 disables RTC).
167 */
168static void icp_timer_start(uint32_t frequency)
169{
170 icp_irqc_mask(ICP_TIMER_IRQ);
171 *((uint32_t *) icp.hw_map.rtc1_load) = frequency;
172 *((uint32_t *) icp.hw_map.rtc1_bgload) = frequency;
173 *((uint32_t *) icp.hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
174 icp_irqc_unmask(ICP_TIMER_IRQ);
175}
176
177static irq_ownership_t icp_timer_claim(irq_t *irq)
178{
179 if (icp.hw_map.rtc1_intrstat) {
180 *((uint32_t *) icp.hw_map.rtc1_intrclr) = 1;
181 return IRQ_ACCEPT;
182 } else
183 return IRQ_DECLINE;
184}
185
186/** Timer interrupt handler.
187 *
188 * @param irq Interrupt information.
189 * @param arg Not used.
190 */
191static void icp_timer_irq_handler(irq_t *irq)
192{
193 /*
194 * We are holding a lock which prevents preemption.
195 * Release the lock, call clock() and reacquire the lock again.
196 */
197
198 spinlock_unlock(&irq->lock);
199 clock();
200 spinlock_lock(&irq->lock);
201
202}
203
204/** Initializes and registers timer interrupt handler. */
205static void icp_timer_irq_init(void)
206{
207 irq_initialize(&icp.timer_irq);
208 icp.timer_irq.inr = ICP_TIMER_IRQ;
209 icp.timer_irq.claim = icp_timer_claim;
210 icp.timer_irq.handler = icp_timer_irq_handler;
211
212 irq_register(&icp.timer_irq);
213}
214
215/** Starts timer.
216 *
217 * Initiates regular timer interrupts after initializing
218 * corresponding interrupt handler.
219 */
220void icp_timer_irq_start(void)
221{
222 icp_timer_irq_init();
223 icp_timer_start(ICP_TIMER_FREQ);
224}
225
226/** Get extents of available memory.
227 *
228 * @param start Place to store memory start address.
229 * @param size Place to store memory size.
230 */
231void icp_get_memory_extents(uintptr_t *start, size_t *size)
232{
233 *start = 0;
234
235 if (hw_map_init_called) {
236 *size = sdram[(*(uint32_t *) icp.hw_map.sdramcr &
237 ICP_SDRAM_MASK) >> 2];
238 } else {
239 *size = SDRAM_SIZE;
240 }
241}
242
243/** Stops icp. */
244void icp_cpu_halt(void)
245{
246 while (1);
247}
248
249/** interrupt exception handler.
250 *
251 * Determines sources of the interrupt from interrupt controller and
252 * calls high-level handlers for them.
253 *
254 * @param exc_no Interrupt exception number.
255 * @param istate Saved processor state.
256 */
257void icp_irq_exception(unsigned int exc_no, istate_t *istate)
258{
259 uint32_t sources = icp_irqc_get_sources();
260 unsigned int i;
261
262 for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) {
263 if (sources & (1 << i)) {
264 irq_t *irq = irq_dispatch_and_lock(i);
265 if (irq) {
266 /* The IRQ handler was found. */
267 irq->handler(irq);
268 spinlock_unlock(&irq->lock);
269 } else {
270 /* Spurious interrupt.*/
271 log(LF_ARCH, LVL_DEBUG,
272 "cpu%d: spurious interrupt (inum=%d)",
273 CPU->id, i);
274 }
275 }
276 }
277}
278
279/*
280 * Integrator specific frame initialization
281 */
282void
283icp_frame_init(void)
284{
285 frame_mark_unavailable(ICP_FB_FRAME, ICP_FB_NUM_FRAME);
286 frame_mark_unavailable(0, 256);
287}
288
289void icp_output_init(void)
290{
291#ifdef CONFIG_FB
292 static bool vga_init = false;
293 if (!vga_init) {
294 icp_vga_init();
295 vga_init = true;
296 }
297
298 fb_properties_t prop = {
299 .addr = ICP_FB,
300 .offset = 0,
301 .x = 640,
302 .y = 480,
303 .scan = 2560,
304 .visual = VISUAL_RGB_8_8_8_0,
305 };
306
307 outdev_t *fbdev = fb_init(&prop);
308 if (fbdev)
309 stdout_wire(fbdev);
310#endif
311#ifdef CONFIG_PL011_UART
312 if (pl011_uart_init(&icp.uart, ICP_UART0_IRQ, ICP_UART))
313 stdout_wire(&icp.uart.outdev);
314#endif
315}
316
317void icp_input_init(void)
318{
319
320 pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC);
321 pl050->status = (ioport8_t *) icp.hw_map.kbd_stat;
322 pl050->data = (ioport8_t *) icp.hw_map.kbd_data;
323 pl050->ctrl = (ioport8_t *) icp.hw_map.kbd_ctrl;
324
325 pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
326 if (pl050_instance) {
327 kbrd_instance_t *kbrd_instance = kbrd_init();
328 if (kbrd_instance) {
329 icp_irqc_mask(ICP_KBD_IRQ);
330 indev_t *sink = stdin_wire();
331 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
332 pl050_wire(pl050_instance, kbrd);
333 icp_irqc_unmask(ICP_KBD_IRQ);
334 }
335 }
336
337 /*
338 * This is the necessary evil until the userspace driver is entirely
339 * self-sufficient.
340 */
341 sysinfo_set_item_val("kbd", NULL, true);
342 sysinfo_set_item_val("kbd.inr", NULL, ICP_KBD_IRQ);
343 sysinfo_set_item_val("kbd.address.physical", NULL, ICP_KBD);
344
345#ifdef CONFIG_PL011_UART
346 srln_instance_t *srln_instance = srln_init();
347 if (srln_instance) {
348 indev_t *sink = stdin_wire();
349 indev_t *srln = srln_wire(srln_instance, sink);
350 pl011_uart_input_wire(&icp.uart, srln);
351 icp_irqc_unmask(ICP_UART0_IRQ);
352 }
353#endif
354}
355
356size_t icp_get_irq_count(void)
357{
358 return ICP_IRQ_COUNT;
359}
360
361const char *icp_get_platform_name(void)
362{
363 return "integratorcp";
364}
365
366/** @}
367 */
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