source: mainline/kernel/arch/arm32/src/mach/integratorcp/integratorcp.c@ cefb126

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cefb126 was 66fcba2, checked in by Jiri Svoboda <jiri@…>, 15 years ago

Do not decide which machine_ops to use at link time.
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1/*
2 * Copyright (c) 2009 Vineeth Pillai
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32integratorcp
30 * @{
31 */
32/** @file
33 * @brief ICP drivers.
34 */
35
36#include <interrupt.h>
37#include <ipc/irq.h>
38#include <console/chardev.h>
39#include <genarch/drivers/pl050/pl050.h>
40#include <genarch/kbrd/kbrd.h>
41#include <console/console.h>
42#include <sysinfo/sysinfo.h>
43#include <print.h>
44#include <ddi/device.h>
45#include <mm/page.h>
46#include <mm/frame.h>
47#include <arch/mm/frame.h>
48#include <arch/mach/integratorcp/integratorcp.h>
49#include <genarch/fb/fb.h>
50#include <genarch/fb/visuals.h>
51#include <ddi/ddi.h>
52#include <print.h>
53
54#define SDRAM_SIZE (sdram[((*(uint32_t *)(ICP_CMCR+ICP_SDRAMCR_OFFSET) & ICP_SDRAM_MASK) >> 2)])
55static parea_t fb_parea;
56static icp_hw_map_t icp_hw_map;
57static irq_t icp_timer_irq;
58struct arm_machine_ops icp_machine_ops = {
59 icp_init,
60 icp_timer_irq_start,
61 icp_cpu_halt,
62 icp_get_memory_size,
63 icp_irq_exception,
64 icp_frame_init,
65 icp_output_init,
66 icp_input_init
67};
68
69static bool hw_map_init_called = false;
70static bool vga_init = false;
71uint32_t sdram[8] = {
72 16777216, /* 16mb */
73 33554432, /* 32mb */
74 67108864, /* 64mb */
75 134217728, /* 128mb */
76 268435456, /* 256mb */
77 0, /* Reserverd */
78 0, /* Reserverd */
79 0 /* Reserverd */
80 };
81
82void icp_vga_init(void);
83
84/** Initializes the vga
85 *
86 */
87void icp_vga_init(void)
88{
89 *(uint32_t*)((char *)(icp_hw_map.cmcr)+0x14) = 0xA05F0000;
90 *(uint32_t*)((char *)(icp_hw_map.cmcr)+0x1C) = 0x12C11000;
91 *(uint32_t*)icp_hw_map.vga = 0x3F1F3F9C;
92 *(uint32_t*)((char *)(icp_hw_map.vga) + 0x4) = 0x080B61DF;
93 *(uint32_t*)((char *)(icp_hw_map.vga) + 0x8) = 0x067F3800;
94 *(uint32_t*)((char *)(icp_hw_map.vga) + 0x10) = ICP_FB;
95 *(uint32_t *)((char *)(icp_hw_map.vga) + 0x1C) = 0x182B;
96 *(uint32_t*)((char *)(icp_hw_map.cmcr)+0xC) = 0x33805000;
97
98}
99
100/** Returns the mask of active interrupts. */
101static inline uint32_t icp_irqc_get_sources(void)
102{
103 return *((uint32_t *) icp_hw_map.irqc);
104}
105
106
107/** Masks interrupt.
108 *
109 * @param irq interrupt number
110 */
111static inline void icp_irqc_mask(uint32_t irq)
112{
113 *((uint32_t *) icp_hw_map.irqc_mask) = (1 << irq);
114}
115
116
117/** Unmasks interrupt.
118 *
119 * @param irq interrupt number
120 */
121static inline void icp_irqc_unmask(uint32_t irq)
122{
123 *((uint32_t *) icp_hw_map.irqc_unmask) |= (1 << irq);
124}
125
126/** Initializes icp_hw_map. */
127void icp_init(void)
128{
129 icp_hw_map.uart = hw_map(ICP_UART, PAGE_SIZE);
130 icp_hw_map.kbd_ctrl = hw_map(ICP_KBD, PAGE_SIZE);
131 icp_hw_map.kbd_stat = icp_hw_map.kbd_ctrl + ICP_KBD_STAT;
132 icp_hw_map.kbd_data = icp_hw_map.kbd_ctrl + ICP_KBD_DATA;
133 icp_hw_map.kbd_intstat = icp_hw_map.kbd_ctrl + ICP_KBD_INTR_STAT;
134 icp_hw_map.rtc = hw_map(ICP_RTC, PAGE_SIZE);
135 icp_hw_map.rtc1_load = icp_hw_map.rtc + ICP_RTC1_LOAD_OFFSET;
136 icp_hw_map.rtc1_read = icp_hw_map.rtc + ICP_RTC1_READ_OFFSET;
137 icp_hw_map.rtc1_ctl = icp_hw_map.rtc + ICP_RTC1_CTL_OFFSET;
138 icp_hw_map.rtc1_intrclr = icp_hw_map.rtc + ICP_RTC1_INTRCLR_OFFSET;
139 icp_hw_map.rtc1_bgload = icp_hw_map.rtc + ICP_RTC1_BGLOAD_OFFSET;
140 icp_hw_map.rtc1_intrstat = icp_hw_map.rtc + ICP_RTC1_INTRSTAT_OFFSET;
141
142 icp_hw_map.irqc = hw_map(ICP_IRQC, PAGE_SIZE);
143 icp_hw_map.irqc_mask = icp_hw_map.irqc + ICP_IRQC_MASK_OFFSET;
144 icp_hw_map.irqc_unmask = icp_hw_map.irqc + ICP_IRQC_UNMASK_OFFSET;
145 icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
146 icp_hw_map.sdramcr = icp_hw_map.cmcr + ICP_SDRAMCR_OFFSET;
147 icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
148
149 hw_map_init_called = true;
150}
151
152/** Starts icp Real Time Clock device, which asserts regular interrupts.
153 *
154 * @param frequency Interrupts frequency (0 disables RTC).
155 */
156static void icp_timer_start(uint32_t frequency)
157{
158 icp_irqc_mask(ICP_TIMER_IRQ);
159 *((uint32_t*) icp_hw_map.rtc1_load) = frequency;
160 *((uint32_t*) icp_hw_map.rtc1_bgload) = frequency;
161 *((uint32_t*) icp_hw_map.rtc1_ctl) = ICP_RTC_CTL_VALUE;
162 icp_irqc_unmask(ICP_TIMER_IRQ);
163}
164
165static irq_ownership_t icp_timer_claim(irq_t *irq)
166{
167 if (icp_hw_map.rtc1_intrstat) {
168 *((uint32_t*) icp_hw_map.rtc1_intrclr) = 1;
169 return IRQ_ACCEPT;
170 } else
171 return IRQ_DECLINE;
172}
173
174/** Timer interrupt handler.
175 *
176 * @param irq Interrupt information.
177 * @param arg Not used.
178 */
179static void icp_timer_irq_handler(irq_t *irq)
180{
181 /*
182 * We are holding a lock which prevents preemption.
183 * Release the lock, call clock() and reacquire the lock again.
184 */
185
186 spinlock_unlock(&irq->lock);
187 clock();
188 spinlock_lock(&irq->lock);
189
190}
191
192/** Initializes and registers timer interrupt handler. */
193static void icp_timer_irq_init(void)
194{
195 irq_initialize(&icp_timer_irq);
196 icp_timer_irq.devno = device_assign_devno();
197 icp_timer_irq.inr = ICP_TIMER_IRQ;
198 icp_timer_irq.claim = icp_timer_claim;
199 icp_timer_irq.handler = icp_timer_irq_handler;
200
201 irq_register(&icp_timer_irq);
202}
203
204
205/** Starts timer.
206 *
207 * Initiates regular timer interrupts after initializing
208 * corresponding interrupt handler.
209 */
210void icp_timer_irq_start(void)
211{
212 icp_timer_irq_init();
213 icp_timer_start(ICP_TIMER_FREQ);
214}
215
216/** Returns the size of emulated memory.
217 *
218 * @return Size in bytes.
219 */
220size_t icp_get_memory_size(void)
221{
222 if (hw_map_init_called) {
223 return (sdram[((*(uint32_t *)icp_hw_map.sdramcr & ICP_SDRAM_MASK) >> 2)]);
224 } else {
225 return SDRAM_SIZE;
226 }
227
228}
229
230/** Stops icp. */
231void icp_cpu_halt(void)
232{
233 while (1);
234}
235
236/** interrupt exception handler.
237 *
238 * Determines sources of the interrupt from interrupt controller and
239 * calls high-level handlers for them.
240 *
241 * @param exc_no Interrupt exception number.
242 * @param istate Saved processor state.
243 */
244void icp_irq_exception(unsigned int exc_no, istate_t *istate)
245{
246 uint32_t sources = icp_irqc_get_sources();
247 unsigned int i;
248
249 for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) {
250 if (sources & (1 << i)) {
251 irq_t *irq = irq_dispatch_and_lock(i);
252 if (irq) {
253 /* The IRQ handler was found. */
254 irq->handler(irq);
255 spinlock_unlock(&irq->lock);
256 } else {
257 /* Spurious interrupt.*/
258 printf("cpu%d: spurious interrupt (inum=%d)\n",
259 CPU->id, i);
260 }
261 }
262 }
263}
264
265/*
266 * Integrator specific frame initialization
267 */
268void
269icp_frame_init(void)
270{
271 frame_mark_unavailable(ICP_FB_FRAME, ICP_FB_NUM_FRAME);
272 frame_mark_unavailable(0, 256);
273}
274
275void icp_output_init(void)
276{
277#ifdef CONFIG_FB
278 if (!vga_init) {
279 icp_vga_init();
280 vga_init = true;
281 }
282
283 fb_properties_t prop = {
284 .addr = ICP_FB,
285 .offset = 0,
286 .x = 640,
287 .y = 480,
288 .scan = 2560,
289 .visual = VISUAL_BGR_0_8_8_8,
290 };
291
292 outdev_t *fbdev = fb_init(&prop);
293 if (fbdev) {
294 stdout_wire(fbdev);
295 fb_parea.pbase = ICP_FB;
296 fb_parea.frames = 300;
297 ddi_parea_register(&fb_parea);
298 }
299#endif
300}
301
302void icp_input_init(void)
303{
304
305 pl050_t *pl050 = malloc(sizeof(pl050_t), FRAME_ATOMIC);
306 pl050->status = (ioport8_t *)icp_hw_map.kbd_stat;
307 pl050->data = (ioport8_t *)icp_hw_map.kbd_data;
308 pl050->ctrl = (ioport8_t *)icp_hw_map.kbd_ctrl;
309
310 pl050_instance_t *pl050_instance = pl050_init(pl050, ICP_KBD_IRQ);
311 if (pl050_instance) {
312 kbrd_instance_t *kbrd_instance = kbrd_init();
313 if (kbrd_instance) {
314 icp_irqc_mask(ICP_KBD_IRQ);
315 indev_t *sink = stdin_wire();
316 indev_t *kbrd = kbrd_wire(kbrd_instance, sink);
317 pl050_wire(pl050_instance, kbrd);
318 icp_irqc_unmask(ICP_KBD_IRQ);
319 }
320 }
321
322 /*
323 * This is the necessary evil until the userspace driver is entirely
324 * self-sufficient.
325 */
326 sysinfo_set_item_val("kbd", NULL, true);
327 sysinfo_set_item_val("kbd.inr", NULL, ICP_KBD_IRQ);
328 sysinfo_set_item_val("kbd.address.status", NULL,
329 (uintptr_t) icp_hw_map.kbd_stat);
330 sysinfo_set_item_val("kbd.address.data", NULL,
331 (uintptr_t) icp_hw_map.kbd_data);
332
333}
334
335
336/** @}
337 */
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