source: mainline/kernel/arch/arm32/src/mach/gta02/gta02.c@ ecf083dd

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ecf083dd was ecf083dd, checked in by Jiri Svoboda <jiri@…>, 15 years ago

Make machine_get_irq_count() a true machine op.

  • Property mode set to 100644
File size: 7.7 KB
Line 
1/*
2 * Copyright (c) 2010 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup arm32gxemul
30 * @{
31 */
32/** @file
33 * @brief Openmoko GTA02 (Neo FreeRunner) platform driver.
34 */
35
36#include <arch/exception.h>
37#include <arch/mach/gta02/gta02.h>
38#include <arch/mm/page.h>
39#include <mm/page.h>
40#include <genarch/fb/fb.h>
41#include <genarch/fb/visuals.h>
42#include <genarch/drivers/s3c24xx_uart/s3c24xx_uart.h>
43#include <genarch/drivers/s3c24xx_irqc/s3c24xx_irqc.h>
44#include <genarch/drivers/s3c24xx_timer/s3c24xx_timer.h>
45#include <genarch/srln/srln.h>
46#include <interrupt.h>
47#include <ddi/ddi.h>
48#include <ddi/device.h>
49
50#define GTA02_MEMORY_START 0x30000000 /* physical */
51#define GTA02_MEMORY_SIZE 0x08000000 /* 128 MB */
52#define GTA02_MEMORY_SKIP 0x8000
53
54/** GTA02 serial console UART address (UART S3C24XX CPU UART channel 2). */
55#define GTA02_SCONS_BASE 0x50008000
56
57/** GTA02 framebuffer base address */
58#define GTA02_FB_BASE 0x08800000
59
60/** IRQ number used for clock */
61#define GTA02_TIMER_IRQ S3C24XX_INT_TIMER0
62
63static void gta02_init(void);
64static void gta02_timer_irq_start(void);
65static void gta02_cpu_halt(void);
66static void gta02_get_memory_extents(uintptr_t *start, uintptr_t *size);
67static void gta02_irq_exception(unsigned int exc_no, istate_t *istate);
68static void gta02_frame_init(void);
69static void gta02_output_init(void);
70static void gta02_input_init(void);
71static size_t gta02_get_irq_count(void);
72
73static void gta02_timer_irq_init(void);
74static void gta02_timer_start(void);
75static irq_ownership_t gta02_timer_irq_claim(irq_t *irq);
76static void gta02_timer_irq_handler(irq_t *irq);
77
78static outdev_t *gta02_scons_dev;
79static s3c24xx_irqc_t gta02_irqc;
80static s3c24xx_timer_t *gta02_timer;
81
82static irq_t gta02_timer_irq;
83
84struct arm_machine_ops gta02_machine_ops = {
85 gta02_init,
86 gta02_timer_irq_start,
87 gta02_cpu_halt,
88 gta02_get_memory_extents,
89 gta02_irq_exception,
90 gta02_frame_init,
91 gta02_output_init,
92 gta02_input_init,
93 gta02_get_irq_count
94};
95
96static void gta02_init(void)
97{
98 s3c24xx_irqc_regs_t *irqc_regs;
99
100 gta02_timer = (void *) hw_map(S3C24XX_TIMER_ADDRESS, PAGE_SIZE);
101 irqc_regs = (void *) hw_map(S3C24XX_IRQC_ADDRESS, PAGE_SIZE);
102
103 /* Initialize interrupt controller. */
104 s3c24xx_irqc_init(&gta02_irqc, irqc_regs);
105}
106
107static void gta02_timer_irq_start(void)
108{
109 gta02_timer_irq_init();
110 gta02_timer_start();
111}
112
113static void gta02_cpu_halt(void)
114{
115}
116
117/** Get extents of available memory.
118 *
119 * @param start Place to store memory start address (physical).
120 * @param size Place to store memory size.
121 */
122static void gta02_get_memory_extents(uintptr_t *start, uintptr_t *size)
123{
124 *start = GTA02_MEMORY_START + GTA02_MEMORY_SKIP;
125 *size = GTA02_MEMORY_SIZE - GTA02_MEMORY_SKIP;
126}
127
128static void gta02_irq_exception(unsigned int exc_no, istate_t *istate)
129{
130 uint32_t inum;
131
132 /* Determine IRQ number. */
133 inum = s3c24xx_irqc_inum_get(&gta02_irqc);
134
135 /* Clear interrupt condition in the interrupt controller. */
136 s3c24xx_irqc_clear(&gta02_irqc, inum);
137
138 irq_t *irq = irq_dispatch_and_lock(inum);
139 if (irq) {
140 /* The IRQ handler was found. */
141 irq->handler(irq);
142 spinlock_unlock(&irq->lock);
143 } else {
144 /* Spurious interrupt.*/
145 printf("cpu%d: spurious interrupt (inum=%d)\n",
146 CPU->id, inum);
147 }
148}
149
150static void gta02_frame_init(void)
151{
152}
153
154static void gta02_output_init(void)
155{
156#ifdef CONFIG_FB
157 parea_t fb_parea;
158
159 fb_properties_t prop = {
160 .addr = GTA02_FB_BASE,
161 .offset = 0,
162 .x = 480,
163 .y = 640,
164 .scan = 960,
165 .visual = VISUAL_RGB_5_6_5_LE
166 };
167
168 outdev_t *fb_dev = fb_init(&prop);
169 if (fb_dev) {
170 stdout_wire(fb_dev);
171 fb_parea.pbase = GTA02_FB_BASE;
172 fb_parea.frames = 150;
173 ddi_parea_register(&fb_parea);
174 }
175#endif
176
177 /* Initialize serial port of the debugging console. */
178 s3c24xx_uart_io_t *scons_io;
179
180 scons_io = (void *) hw_map(GTA02_SCONS_BASE, PAGE_SIZE);
181 gta02_scons_dev = s3c24xx_uart_init(scons_io, S3C24XX_INT_UART2);
182
183 if (gta02_scons_dev) {
184 /* Create output device. */
185 stdout_wire(gta02_scons_dev);
186 }
187}
188
189static void gta02_input_init(void)
190{
191 s3c24xx_uart_t *scons_inst;
192
193 if (gta02_scons_dev) {
194 /* Create input device. */
195 scons_inst = (void *) gta02_scons_dev->data;
196
197 srln_instance_t *srln_instance = srln_init();
198 if (srln_instance) {
199 indev_t *sink = stdin_wire();
200 indev_t *srln = srln_wire(srln_instance, sink);
201 s3c24xx_uart_input_wire(scons_inst, srln);
202
203 /* Enable interrupts from UART2 */
204 s3c24xx_irqc_src_enable(&gta02_irqc,
205 S3C24XX_INT_UART2);
206
207 /* Enable interrupts from UART2 RXD */
208 s3c24xx_irqc_subsrc_enable(&gta02_irqc,
209 S3C24XX_SUBINT_RXD2);
210 }
211 }
212}
213
214size_t gta02_get_irq_count(void)
215{
216 return GTA02_IRQ_COUNT;
217}
218
219static void gta02_timer_irq_init(void)
220{
221 irq_initialize(&gta02_timer_irq);
222 gta02_timer_irq.devno = device_assign_devno();
223 gta02_timer_irq.inr = GTA02_TIMER_IRQ;
224 gta02_timer_irq.claim = gta02_timer_irq_claim;
225 gta02_timer_irq.handler = gta02_timer_irq_handler;
226
227 irq_register(&gta02_timer_irq);
228}
229
230static irq_ownership_t gta02_timer_irq_claim(irq_t *irq)
231{
232 return IRQ_ACCEPT;
233}
234
235static void gta02_timer_irq_handler(irq_t *irq)
236{
237 /*
238 * We are holding a lock which prevents preemption.
239 * Release the lock, call clock() and reacquire the lock again.
240 */
241 spinlock_unlock(&irq->lock);
242 clock();
243 spinlock_lock(&irq->lock);
244}
245
246static void gta02_timer_start(void)
247{
248 s3c24xx_timer_t *timer = gta02_timer;
249
250 /*
251 * See S3C2442B user manual chapter 10 (PWM Timer) for description
252 * of timer operation. Starting a timer is described in the
253 * section 'Timer initialization using manual update bit and
254 * inverter bit'.
255 */
256
257 /*
258 * GTA02 PCLK should be 100 MHz.
259 * Timer input freq. = PCLK / divider / (1+prescaler)
260 * 100 MHz / 2 / (1+7) / 62500 ~= 100 Hz
261 */
262#if HZ != 100
263#warning Other HZ than 100 not suppored.
264#endif
265
266 /* Set prescaler values. No pre-divison, no dead zone. */
267 pio_write_32(&timer->tcfg0, 7); /* prescale 1/8 */
268
269 /* No DMA request, divider value = 2 for all timers. */
270 pio_write_32(&timer->tcfg1, 0);
271
272 /* Stop all timers. */
273 pio_write_32(&timer->tcon, 0);
274
275 /* Start counting from 64k-1. Compare value is irrelevant. */
276 pio_write_32(&timer->timer[0].cntb, 62500);
277 pio_write_32(&timer->timer[0].cmpb, 0);
278
279 /* Enable interrupts from timer0 */
280 s3c24xx_irqc_src_enable(&gta02_irqc, S3C24XX_INT_TIMER0);
281
282 /* Load data from tcntb0/tcmpb0 into tcnt0/tcmp0. */
283 pio_write_32(&timer->tcon, TCON_T0_AUTO_RLD | TCON_T0_MUPDATE);
284
285 /* Start timer 0. Inverter is off. */
286 pio_write_32(&timer->tcon, TCON_T0_AUTO_RLD | TCON_T0_START);
287}
288
289/** @}
290 */
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