source: mainline/kernel/arch/arm32/src/mach/beaglebone/beaglebone.c@ b67ce1ff

ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b67ce1ff was b67ce1ff, checked in by Jiří Zárevúcky <zarevucky.jiri@…>, 2 years ago

Use irq_spinlock functions in arm32 code, to be consistent with all other code

  • Property mode set to 100644
File size: 6.8 KB
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1/*
2 * Copyright (c) 2012 Matteo Facchinetti
3 * Copyright (c) 2012 Maurizio Lombardi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29/** @addtogroup kernel_arm32_beaglebone
30 * @{
31 */
32/** @file
33 * @brief BeagleBone platform driver.
34 */
35
36#include <arch/exception.h>
37#include <arch/mach/beaglebone/beaglebone.h>
38#include <assert.h>
39#include <genarch/drivers/am335x/irc.h>
40#include <genarch/drivers/am335x/uart.h>
41#include <genarch/drivers/am335x/timer.h>
42#include <genarch/drivers/am335x/cm_per.h>
43#include <genarch/drivers/am335x/cm_dpll.h>
44#include <genarch/drivers/am335x/ctrl_module.h>
45#include <genarch/srln/srln.h>
46#include <interrupt.h>
47#include <ddi/ddi.h>
48#include <mm/km.h>
49#include <stdbool.h>
50
51#define BBONE_MEMORY_START 0x80000000 /* physical */
52#define BBONE_MEMORY_SIZE 0x10000000 /* 256 MB */
53
54static void bbone_init(void);
55static void bbone_timer_irq_start(void);
56static void bbone_cpu_halt(void);
57static void bbone_get_memory_extents(uintptr_t *start, size_t *size);
58static void bbone_irq_exception(unsigned int exc_no, istate_t *istate);
59static void bbone_frame_init(void);
60static void bbone_output_init(void);
61static void bbone_input_init(void);
62static size_t bbone_get_irq_count(void);
63static const char *bbone_get_platform_name(void);
64
65static struct beaglebone {
66 omap_irc_regs_t *irc_addr;
67 am335x_cm_per_regs_t *cm_per_addr;
68 am335x_cm_dpll_regs_t *cm_dpll_addr;
69 am335x_ctrl_module_t *ctrl_module;
70 am335x_timer_t timer;
71 omap_uart_t uart;
72} bbone;
73
74struct arm_machine_ops bbone_machine_ops = {
75 .machine_init = bbone_init,
76 .machine_timer_irq_start = bbone_timer_irq_start,
77 .machine_cpu_halt = bbone_cpu_halt,
78 .machine_get_memory_extents = bbone_get_memory_extents,
79 .machine_irq_exception = bbone_irq_exception,
80 .machine_frame_init = bbone_frame_init,
81 .machine_output_init = bbone_output_init,
82 .machine_input_init = bbone_input_init,
83 .machine_get_irq_count = bbone_get_irq_count,
84 .machine_get_platform_name = bbone_get_platform_name,
85};
86
87static void bbone_init(void)
88{
89 bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS,
90 AM335x_IRC_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
91
92 bbone.cm_per_addr = (void *) km_map(AM335x_CM_PER_BASE_ADDRESS,
93 AM335x_CM_PER_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
94
95 bbone.cm_dpll_addr = (void *) km_map(AM335x_CM_DPLL_BASE_ADDRESS,
96 AM335x_CM_DPLL_SIZE, KM_NATURAL_ALIGNMENT, PAGE_NOT_CACHEABLE);
97
98 bbone.ctrl_module = (void *) km_map(AM335x_CTRL_MODULE_BASE_ADDRESS,
99 AM335x_CTRL_MODULE_SIZE, KM_NATURAL_ALIGNMENT,
100 PAGE_NOT_CACHEABLE);
101
102 assert(bbone.irc_addr != NULL);
103 assert(bbone.cm_per_addr != NULL);
104 assert(bbone.cm_dpll_addr != NULL);
105 assert(bbone.ctrl_module != NULL);
106
107 /* Initialize the interrupt controller */
108 omap_irc_init(bbone.irc_addr);
109}
110
111static irq_ownership_t bbone_timer_irq_claim(irq_t *irq)
112{
113 return IRQ_ACCEPT;
114}
115
116static void bbone_timer_irq_handler(irq_t *irq)
117{
118 am335x_timer_intr_ack(&bbone.timer);
119 irq_spinlock_unlock(&irq->lock, false);
120 clock();
121 irq_spinlock_lock(&irq->lock, false);
122}
123
124static void bbone_timer_irq_start(void)
125{
126 unsigned sysclk_freq;
127 errno_t rc;
128
129 /* Initialize the IRQ */
130 static irq_t timer_irq;
131 irq_initialize(&timer_irq);
132 timer_irq.inr = AM335x_DMTIMER2_IRQ;
133 timer_irq.claim = bbone_timer_irq_claim;
134 timer_irq.handler = bbone_timer_irq_handler;
135 irq_register(&timer_irq);
136
137 /* Enable the DMTIMER2 clock module */
138 am335x_clock_module_enable(bbone.cm_per_addr, DMTIMER2);
139 /* Select the SYSCLK as the clock source for the dmtimer2 module */
140 am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2,
141 CLK_SRC_M_OSC);
142 /* Initialize the DMTIMER2 */
143 if (am335x_ctrl_module_clock_freq_get(bbone.ctrl_module,
144 &sysclk_freq) != EOK) {
145 printf("Cannot get the system clock frequency!\n");
146 return;
147 } else
148 printf("system clock running at %u hz\n", sysclk_freq);
149
150 rc = am335x_timer_init(&bbone.timer, DMTIMER2, HZ, sysclk_freq);
151 if (rc != EOK) {
152 printf("Timer initialization failed\n");
153 return;
154 }
155 /* Enable the interrupt */
156 omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
157 /* Start the timer */
158 am335x_timer_start(&bbone.timer);
159}
160
161static void bbone_cpu_halt(void)
162{
163 while (true)
164 ;
165}
166
167/** Get extents of available memory.
168 *
169 * @param start Place to store memory start address (physical).
170 * @param size Place to store memory size.
171 */
172static void bbone_get_memory_extents(uintptr_t *start, size_t *size)
173{
174 *start = BBONE_MEMORY_START;
175 *size = BBONE_MEMORY_SIZE;
176}
177
178static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
179{
180 const unsigned inum = omap_irc_inum_get(bbone.irc_addr);
181
182 irq_t *irq = irq_dispatch_and_lock(inum);
183 if (irq) {
184 /* The IRQ handler was found. */
185 irq->handler(irq);
186 irq_spinlock_unlock(&irq->lock, false);
187 } else {
188 printf("Spurious interrupt\n");
189 }
190
191 omap_irc_irq_ack(bbone.irc_addr);
192}
193
194static void bbone_frame_init(void)
195{
196}
197
198static void bbone_output_init(void)
199{
200#ifdef CONFIG_OMAP_UART
201 const bool ok = omap_uart_init(&bbone.uart,
202 AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
203 AM335x_UART0_SIZE);
204
205 if (ok)
206 stdout_wire(&bbone.uart.outdev);
207#endif
208}
209
210static void bbone_input_init(void)
211{
212#ifdef CONFIG_OMAP_UART
213 srln_instance_t *srln_instance = srln_init();
214 if (srln_instance) {
215 indev_t *sink = stdin_wire();
216 indev_t *srln = srln_wire(srln_instance, sink);
217 omap_uart_input_wire(&bbone.uart, srln);
218 omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
219 }
220#endif
221}
222
223size_t bbone_get_irq_count(void)
224{
225 return AM335x_IRC_IRQ_COUNT;
226}
227
228const char *bbone_get_platform_name(void)
229{
230 return "beaglebone";
231}
232
233/**
234 * @}
235 */
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